[Mesa-dev] [PATCH 22/25] i965/gen6+: Factor out PIPE_CONTROL submission from intel_batchbuffer_emit_mi_flush.

[Francisco Jerez]

---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 54 ++++++++++++++++-----------
 src/mesa/drivers/dri/i965/intel_batchbuffer.h |  2 +
 2 files changed, 34 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 25aacd9..d11de49 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -633,6 +633,30 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
    brw->batch.need_workaround_flush = false;
 }
 
+void
+intel_batchbuffer_emit_pipe_control(struct brw_context *brw,
+                                    unsigned bits)
+{
+   assert(brw->gen >= 6);
+
+   if (brw->gen == 6) {
+      /* Hardware workaround: SNB B-Spec says:
+       *
+       * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
+       * Enable =1, a PIPE_CONTROL with any non-zero post-sync-op is
+       * required.
+       */
+      intel_emit_post_sync_nonzero_flush(brw);
+   }
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
+   OUT_BATCH(bits);
+   OUT_BATCH(0); /* write address */
+   OUT_BATCH(0); /* write data */
+   ADVANCE_BATCH();
+}
+
 /* Emit a pipelined flush to either flush render and texture cache for
  * reading from a FBO-drawn texture, or flush so that frontbuffer
  * render appears on the screen in DRI1.
@@ -651,28 +675,14 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
 	 OUT_BATCH(0);
 	 ADVANCE_BATCH();
       } else {
-	 if (brw->gen == 6) {
-	    /* Hardware workaround: SNB B-Spec says:
-	     *
-	     * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
-	     * Flush Enable =1, a PIPE_CONTROL with any non-zero
-	     * post-sync-op is required.
-	     */
-	    intel_emit_post_sync_nonzero_flush(brw);
-	 }
-
-	 BEGIN_BATCH(4);
-	 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
-	 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
-		   PIPE_CONTROL_WRITE_FLUSH |
-		   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                   PIPE_CONTROL_VF_CACHE_INVALIDATE |
-		   PIPE_CONTROL_TC_FLUSH |
-		   PIPE_CONTROL_NO_WRITE |
-                   PIPE_CONTROL_CS_STALL);
-	 OUT_BATCH(0); /* write address */
-	 OUT_BATCH(0); /* write data */
-	 ADVANCE_BATCH();
+         intel_batchbuffer_emit_pipe_control(
+            brw, (PIPE_CONTROL_INSTRUCTION_FLUSH |
+                  PIPE_CONTROL_WRITE_FLUSH |
+                  PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                  PIPE_CONTROL_VF_CACHE_INVALIDATE |
+                  PIPE_CONTROL_TC_FLUSH |
+                  PIPE_CONTROL_NO_WRITE |
+                  PIPE_CONTROL_CS_STALL));
       }
    } else {
       BEGIN_BATCH(4);
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index ac8eb7d..c561149 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -65,6 +65,8 @@ bool intel_batchbuffer_emit_reloc_fenced(struct brw_context *brw,
 					      uint32_t write_domain,
 					      uint32_t offset);
 void intel_batchbuffer_emit_mi_flush(struct brw_context *brw);
+void intel_batchbuffer_emit_pipe_control(struct brw_context *brw,
+                                         unsigned flush_bits);
 void intel_emit_post_sync_nonzero_flush(struct brw_context *brw);
 void intel_emit_depth_stall_flushes(struct brw_context *brw);
 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
-- 
1.8.3.4