[Mesa-dev] PATCHES: R600: Register machine passes and code cleanups
Tom Stellard
tom at stellard.net
Mon Dec 9 08:02:58 PST 2013
Hi,
The first two patches register the R600EmitClauseMarkers and
AMDGPUCFGStructurizer passes, so that -print-*-all will now work with
them. The third patch is a cleanup of Processors.td and the fourth
patch adds the wavefront size property to the subtargets.
Please Review.
-Tom
-------------- next part --------------
>From 28e45d4418b7a086651aaba3eda1150472aca928 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Mon, 2 Dec 2013 12:37:14 -0800
Subject: [PATCH 1/4] R600: Register R600EmitClauseMarkers pass
This enables -print-before-all to dump MachineInstrs after it is run.
---
lib/Target/R600/AMDGPU.h | 2 +-
lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +-
lib/Target/R600/R600EmitClauseMarkers.cpp | 24 +++++++++++++++++-------
3 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/lib/Target/R600/AMDGPU.h b/lib/Target/R600/AMDGPU.h
index 025b28e..e73bde1 100644
--- a/lib/Target/R600/AMDGPU.h
+++ b/lib/Target/R600/AMDGPU.h
@@ -28,7 +28,7 @@ class TargetMachine;
FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
FunctionPass *createR600TextureIntrinsicsReplacer();
FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
-FunctionPass *createR600EmitClauseMarkers(TargetMachine &tm);
+FunctionPass *createR600EmitClauseMarkers();
FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
FunctionPass *createR600Packetizer(TargetMachine &tm);
FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp
index bc4f5d7..adf5758 100644
--- a/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -167,7 +167,7 @@ bool AMDGPUPassConfig::addPreSched2() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
- addPass(createR600EmitClauseMarkers(*TM));
+ addPass(createR600EmitClauseMarkers());
if (ST.isIfCvtEnabled())
addPass(&IfConverterID);
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
diff --git a/lib/Target/R600/R600EmitClauseMarkers.cpp b/lib/Target/R600/R600EmitClauseMarkers.cpp
index 1bbfd2b..5bd793a 100644
--- a/lib/Target/R600/R600EmitClauseMarkers.cpp
+++ b/lib/Target/R600/R600EmitClauseMarkers.cpp
@@ -25,12 +25,15 @@
using namespace llvm;
+namespace llvm {
+ void initializeR600EmitClauseMarkersPass(PassRegistry&);
+}
+
namespace {
-class R600EmitClauseMarkersPass : public MachineFunctionPass {
+class R600EmitClauseMarkers : public MachineFunctionPass {
private:
- static char ID;
const R600InstrInfo *TII;
int Address;
@@ -287,8 +290,11 @@ private:
}
public:
- R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
- TII(0), Address(0) { }
+ static char ID;
+ R600EmitClauseMarkers() : MachineFunctionPass(ID), TII(0), Address(0) {
+
+ initializeR600EmitClauseMarkersPass(*PassRegistry::getPassRegistry());
+ }
virtual bool runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
@@ -314,12 +320,16 @@ public:
}
};
-char R600EmitClauseMarkersPass::ID = 0;
+char R600EmitClauseMarkers::ID = 0;
} // end anonymous namespace
+INITIALIZE_PASS_BEGIN(R600EmitClauseMarkers, "emitclausemarkers",
+ "R600 Emit Clause Markters", false, false)
+INITIALIZE_PASS_END(R600EmitClauseMarkers, "emitclausemarkers",
+ "R600 Emit Clause Markters", false, false)
-llvm::FunctionPass *llvm::createR600EmitClauseMarkers(TargetMachine &TM) {
- return new R600EmitClauseMarkersPass(TM);
+llvm::FunctionPass *llvm::createR600EmitClauseMarkers() {
+ return new R600EmitClauseMarkers();
}
--
1.8.1.4
-------------- next part --------------
>From aae06f55c3286e720c1fe584445d2e3d769cc5bc Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Tue, 3 Dec 2013 17:59:03 -0800
Subject: [PATCH 2/4] R600: Register AMDGPUCFGStructurizer pass
This enables -print-before-all to dump MachineInstrs after it is run.
---
lib/Target/R600/AMDGPU.h | 2 +-
lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +-
lib/Target/R600/AMDILCFGStructurizer.cpp | 29 +++++++++++++++++++++--------
3 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/lib/Target/R600/AMDGPU.h b/lib/Target/R600/AMDGPU.h
index e73bde1..8eb1b69 100644
--- a/lib/Target/R600/AMDGPU.h
+++ b/lib/Target/R600/AMDGPU.h
@@ -32,7 +32,7 @@ FunctionPass *createR600EmitClauseMarkers();
FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
FunctionPass *createR600Packetizer(TargetMachine &tm);
FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
-FunctionPass *createAMDGPUCFGStructurizerPass(TargetMachine &tm);
+FunctionPass *createAMDGPUCFGStructurizerPass();
// SI Passes
FunctionPass *createSITypeRewriter();
diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp
index adf5758..404eb89 100644
--- a/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -178,7 +178,7 @@ bool AMDGPUPassConfig::addPreSched2() {
bool AMDGPUPassConfig::addPreEmitPass() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
- addPass(createAMDGPUCFGStructurizerPass(*TM));
+ addPass(createAMDGPUCFGStructurizerPass());
addPass(createR600ExpandSpecialInstrsPass(*TM));
addPass(&FinalizeMachineBundlesID);
addPass(createR600Packetizer(*TM));
diff --git a/lib/Target/R600/AMDILCFGStructurizer.cpp b/lib/Target/R600/AMDILCFGStructurizer.cpp
index 507570f..92ce82f 100644
--- a/lib/Target/R600/AMDILCFGStructurizer.cpp
+++ b/lib/Target/R600/AMDILCFGStructurizer.cpp
@@ -54,6 +54,10 @@ STATISTIC(numLoopcontPatternMatch, "CFGStructurizer number of loop-continue "
STATISTIC(numClonedBlock, "CFGStructurizer cloned blocks");
STATISTIC(numClonedInstr, "CFGStructurizer cloned instructions");
+namespace llvm {
+ void initializeAMDGPUCFGStructurizerPass(PassRegistry&);
+}
+
//===----------------------------------------------------------------------===//
//
// Miscellaneous utility for CFGStructurizer.
@@ -131,13 +135,13 @@ public:
static char ID;
- AMDGPUCFGStructurizer(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm),
- TII(static_cast<const R600InstrInfo *>(tm.getInstrInfo())),
- TRI(&TII->getRegisterInfo()) { }
+ AMDGPUCFGStructurizer() :
+ MachineFunctionPass(ID), TII(NULL), TRI(NULL) {
+ initializeAMDGPUCFGStructurizerPass(*PassRegistry::getPassRegistry());
+ }
const char *getPassName() const {
- return "AMD IL Control Flow Graph structurizer Pass";
+ return "AMDGPU Control Flow Graph structurizer Pass";
}
void getAnalysisUsage(AnalysisUsage &AU) const {
@@ -157,6 +161,8 @@ public:
bool prepare();
bool runOnMachineFunction(MachineFunction &MF) {
+ TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
+ TRI = &TII->getRegisterInfo();
DEBUG(MF.dump(););
OrderedBlks.clear();
FuncRep = &MF;
@@ -173,7 +179,6 @@ public:
}
protected:
- TargetMachine &TM;
MachineDominatorTree *MDT;
MachinePostDominatorTree *PDT;
MachineLoopInfo *MLI;
@@ -1899,6 +1904,14 @@ char AMDGPUCFGStructurizer::ID = 0;
} // end anonymous namespace
-FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm) {
- return new AMDGPUCFGStructurizer(tm);
+INITIALIZE_PASS_BEGIN(AMDGPUCFGStructurizer, "amdgpustructurizer",
+ "AMDGPU CFG Structurizer", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
+INITIALIZE_PASS_END(AMDGPUCFGStructurizer, "amdgpustructurizer",
+ "AMDGPU CFG Structurizer", false, false)
+
+FunctionPass *llvm::createAMDGPUCFGStructurizerPass() {
+ return new AMDGPUCFGStructurizer();
}
--
1.8.1.4
-------------- next part --------------
>From cc8bdff700e6896c2f21e9fab8ad925d4da55bc4 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Thu, 5 Dec 2013 15:40:21 -0800
Subject: [PATCH 3/4] R600: Re-format Processors.td
This makes it a little easier to read.
---
lib/Target/R600/Processors.td | 48 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
index ee190e4..5499a20 100644
--- a/lib/Target/R600/Processors.td
+++ b/lib/Target/R600/Processors.td
@@ -9,46 +9,94 @@
class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
: Processor<Name, itin, Features>;
+
+//===----------------------------------------------------------------------===//
+// R600
+//===----------------------------------------------------------------------===//
def : Proc<"", R600_VLIW5_Itin,
[FeatureR600, FeatureVertexCache]>;
+
def : Proc<"r600", R600_VLIW5_Itin,
[FeatureR600 , FeatureVertexCache]>;
+
def : Proc<"rs880", R600_VLIW5_Itin,
[FeatureR600]>;
+
def : Proc<"rv670", R600_VLIW5_Itin,
[FeatureR600, FeatureFP64, FeatureVertexCache]>;
+
+//===----------------------------------------------------------------------===//
+// R700
+//===----------------------------------------------------------------------===//
+
def : Proc<"rv710", R600_VLIW5_Itin,
[FeatureR700, FeatureVertexCache]>;
+
def : Proc<"rv730", R600_VLIW5_Itin,
[FeatureR700, FeatureVertexCache]>;
+
def : Proc<"rv770", R600_VLIW5_Itin,
[FeatureR700, FeatureFP64, FeatureVertexCache]>;
+
+//===----------------------------------------------------------------------===//
+// Evergreen
+//===----------------------------------------------------------------------===//
+
def : Proc<"cedar", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureVertexCache]>;
+
def : Proc<"redwood", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureVertexCache]>;
+
def : Proc<"sumo", R600_VLIW5_Itin,
[FeatureEvergreen]>;
+
def : Proc<"juniper", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureVertexCache]>;
+
def : Proc<"cypress", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureFP64, FeatureVertexCache]>;
+
+//===----------------------------------------------------------------------===//
+// Northern Islands
+//===----------------------------------------------------------------------===//
+
def : Proc<"barts", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureVertexCache]>;
+
def : Proc<"turks", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureVertexCache]>;
+
def : Proc<"caicos", R600_VLIW5_Itin,
[FeatureNorthernIslands]>;
+
def : Proc<"cayman", R600_VLIW4_Itin,
[FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
+//===----------------------------------------------------------------------===//
+// Southern Islands
+//===----------------------------------------------------------------------===//
+
def : Proc<"SI", SI_Itin, [FeatureSouthernIslands]>;
+
def : Proc<"tahiti", SI_Itin, [FeatureSouthernIslands]>;
+
def : Proc<"pitcairn", SI_Itin, [FeatureSouthernIslands]>;
+
def : Proc<"verde", SI_Itin, [FeatureSouthernIslands]>;
+
def : Proc<"oland", SI_Itin, [FeatureSouthernIslands]>;
+
def : Proc<"hainan", SI_Itin, [FeatureSouthernIslands]>;
+
+//===----------------------------------------------------------------------===//
+// Sea Islands
+//===----------------------------------------------------------------------===//
+
def : Proc<"bonaire", SI_Itin, [FeatureSeaIslands]>;
+
def : Proc<"kabini", SI_Itin, [FeatureSeaIslands]>;
+
def : Proc<"kaveri", SI_Itin, [FeatureSeaIslands]>;
+
def : Proc<"hawaii", SI_Itin, [FeatureSeaIslands]>;
--
1.8.1.4
-------------- next part --------------
>From 1ecfe00ed4a3f1c1188c7e570047ab1e8397a6ca Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Thu, 5 Dec 2013 18:59:51 -0800
Subject: [PATCH 4/4] R600: Add wavefront size property to the subtargets
---
lib/Target/R600/AMDGPU.td | 12 +++++++++++-
lib/Target/R600/AMDGPUSubtarget.cpp | 5 +++++
lib/Target/R600/AMDGPUSubtarget.h | 2 ++
lib/Target/R600/Processors.td | 26 +++++++++++++++-----------
4 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
index 182235b..df64f47 100644
--- a/lib/Target/R600/AMDGPU.td
+++ b/lib/Target/R600/AMDGPU.td
@@ -72,6 +72,16 @@ class SubtargetFeatureFetchLimit <string Value> :
def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
+class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
+ "wavefrontsize"#Value,
+ "WavefrontSize",
+ !cast<string>(Value),
+ "The number of threads per wavefront">;
+
+def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
+def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
+def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
+
class SubtargetFeatureGeneration <string Value,
list<SubtargetFeature> Implies> :
SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
@@ -87,7 +97,7 @@ def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
[FeatureFetchLimit16]>;
def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
- [FeatureFetchLimit16]>;
+ [FeatureFetchLimit16, FeatureWavefrontSize64]>;
def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
[Feature64BitPtr, FeatureFP64]>;
diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp
index 061793a..74bdb44 100644
--- a/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -38,6 +38,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
CaymanISA = false;
EnableIRStructurizer = true;
EnableIfCvt = true;
+ WavefrontSize = 64;
ParseSubtargetFeatures(GPU, FS);
DevName = GPU;
}
@@ -74,6 +75,10 @@ bool
AMDGPUSubtarget::isIfCvtEnabled() const {
return EnableIfCvt;
}
+unsigned
+AMDGPUSubtarget::getWavefrontSize() const {
+ return WavefrontSize;
+}
bool
AMDGPUSubtarget::isTargetELF() const {
return false;
diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h
index 4288d27..7c122a8 100644
--- a/lib/Target/R600/AMDGPUSubtarget.h
+++ b/lib/Target/R600/AMDGPUSubtarget.h
@@ -51,6 +51,7 @@ private:
bool CaymanISA;
bool EnableIRStructurizer;
bool EnableIfCvt;
+ unsigned WavefrontSize;
InstrItineraryData InstrItins;
@@ -68,6 +69,7 @@ public:
bool hasCaymanISA() const;
bool IsIRStructurizerEnabled() const;
bool isIfCvtEnabled() const;
+ unsigned getWavefrontSize() const;
virtual bool enableMachineScheduler() const {
return getGeneration() <= NORTHERN_ISLANDS;
diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
index 5499a20..e601f35 100644
--- a/lib/Target/R600/Processors.td
+++ b/lib/Target/R600/Processors.td
@@ -17,45 +17,49 @@ def : Proc<"", R600_VLIW5_Itin,
[FeatureR600, FeatureVertexCache]>;
def : Proc<"r600", R600_VLIW5_Itin,
- [FeatureR600 , FeatureVertexCache]>;
+ [FeatureR600 , FeatureVertexCache, FeatureWavefrontSize64]>;
+
+def : Proc<"r630", R600_VLIW5_Itin,
+ [FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;
def : Proc<"rs880", R600_VLIW5_Itin,
- [FeatureR600]>;
+ [FeatureR600, FeatureWavefrontSize16]>;
def : Proc<"rv670", R600_VLIW5_Itin,
- [FeatureR600, FeatureFP64, FeatureVertexCache]>;
+ [FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
//===----------------------------------------------------------------------===//
// R700
//===----------------------------------------------------------------------===//
def : Proc<"rv710", R600_VLIW5_Itin,
- [FeatureR700, FeatureVertexCache]>;
+ [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
def : Proc<"rv730", R600_VLIW5_Itin,
- [FeatureR700, FeatureVertexCache]>;
+ [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
def : Proc<"rv770", R600_VLIW5_Itin,
- [FeatureR700, FeatureFP64, FeatureVertexCache]>;
+ [FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
//===----------------------------------------------------------------------===//
// Evergreen
//===----------------------------------------------------------------------===//
def : Proc<"cedar", R600_VLIW5_Itin,
- [FeatureEvergreen, FeatureVertexCache]>;
+ [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32]>;
def : Proc<"redwood", R600_VLIW5_Itin,
- [FeatureEvergreen, FeatureVertexCache]>;
+ [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
def : Proc<"sumo", R600_VLIW5_Itin,
- [FeatureEvergreen]>;
+ [FeatureEvergreen, FeatureWavefrontSize64]>;
def : Proc<"juniper", R600_VLIW5_Itin,
- [FeatureEvergreen, FeatureVertexCache]>;
+ [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
def : Proc<"cypress", R600_VLIW5_Itin,
- [FeatureEvergreen, FeatureFP64, FeatureVertexCache]>;
+ [FeatureEvergreen, FeatureFP64, FeatureVertexCache,
+ FeatureWavefrontSize64]>;
//===----------------------------------------------------------------------===//
// Northern Islands
--
1.8.1.4
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