[Mesa-dev] [PATCH 1/3] radeon: rearrange r600_texture and related code a bit.
Andreas Hartmetz
ahartmetz at gmail.com
Tue Dec 10 12:15:28 PST 2013
This should make the differences and similarities between color and
depth buffer handling more clear.
---
src/gallium/drivers/r600/evergreen_state.c | 10 ++---
src/gallium/drivers/r600/r600_blit.c | 6 +--
src/gallium/drivers/r600/r600_state.c | 10 ++---
src/gallium/drivers/radeon/r600_pipe_common.h | 8 ++--
src/gallium/drivers/radeon/r600_texture.c | 58 +++++++++++++--------------
5 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index a4a4e3e..0342574 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1696,8 +1696,8 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
surf->htile_enabled = 0;
/* use htile only for first level */
- if (rtex->htile && !level) {
- uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile->b.b);
+ if (rtex->htile_buffer && !level) {
+ uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
surf->htile_enabled = 1;
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
@@ -1732,7 +1732,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
- if (rtex->htile) {
+ if (rtex->htile_buffer) {
rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
}
}
@@ -2362,11 +2362,11 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom
struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
unsigned reloc_idx;
- r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
+ r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
- reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
+ reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE);
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
cs->buf[cs->cdw++] = reloc_idx;
} else {
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index f33bb43..42034a0 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -547,9 +547,9 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
* disable fast clear for texture array.
*/
/* Only use htile for first level */
- if (rtex->htile && !level && rtex->surface.array_size == 1) {
- if (rtex->depth_clear != depth) {
- rtex->depth_clear = depth;
+ if (rtex->htile_buffer && !level && rtex->surface.array_size == 1) {
+ if (rtex->depth_clear_value != depth) {
+ rtex->depth_clear_value = depth;
rctx->db_state.atom.dirty = true;
}
rctx->db_misc_state.htile_clear = true;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 41e9c5d..2cff22c 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1533,8 +1533,8 @@ static void r600_init_depth_surface(struct r600_context *rctx,
surf->htile_enabled = 0;
/* use htile only for first level */
- if (rtex->htile && !level) {
- uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile->b.b);
+ if (rtex->htile_buffer && !level) {
+ uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
surf->htile_enabled = 1;
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
@@ -1570,7 +1570,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
- if (rctx->b.chip_class >= R700 && rtex->htile) {
+ if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
}
}
@@ -2010,10 +2010,10 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom
struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
unsigned reloc_idx;
- r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
+ r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
- reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
+ reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE);
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
cs->buf[cs->cdw++] = reloc_idx;
} else {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index f0fcaac..31bb879 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -136,13 +136,13 @@ struct r600_texture {
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info fmask;
struct r600_cmask_info cmask;
-
- struct r600_resource *htile;
- float depth_clear; /* use htile only for first level */
-
struct r600_resource *cmask_buffer;
unsigned color_clear_value[2];
+ /* Depth buffer compression and fast clear. */
+ struct r600_resource *htile_buffer;
+ float depth_clear_value;
+
bool non_disp_tiling; /* R600-Cayman only */
unsigned mipmap_shift;
};
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 99f8445..e7ce103 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -269,7 +269,7 @@ static void r600_texture_destroy(struct pipe_screen *screen,
if (rtex->flushed_depth_texture)
pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
- pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
+ pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
if (rtex->cmask_buffer != &rtex->resource) {
pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
}
@@ -482,18 +482,19 @@ static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
htile_size = align(htile_size, (2 << 10) * npipes);
/* XXX don't allocate it separately */
- rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC, htile_size);
- if (rtex->htile == NULL) {
+ rtex->htile_buffer = (struct r600_resource*)pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_STATIC, htile_size);
+ if (rtex->htile_buffer == NULL) {
/* this is not a fatal error as we can still keep rendering
* without htile buffer
*/
R600_ERR("r600: failed to create bo for htile buffers\n");
} else {
- r600_screen_clear_buffer(rscreen, &rtex->htile->b.b, 0, htile_size, 0);
+ r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0, htile_size, 0);
}
}
+/* Common processing for r600_texture_create and r600_texture_from_handle */
static struct r600_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
@@ -504,7 +505,6 @@ r600_texture_create_object(struct pipe_screen *screen,
struct r600_texture *rtex;
struct r600_resource *resource;
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
- int r;
rtex = CALLOC_STRUCT(r600_texture);
if (rtex == NULL)
@@ -521,8 +521,7 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
rtex->surface = *surface;
- r = r600_setup_surface(screen, rtex, pitch_in_bytes_override);
- if (r) {
+ if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
FREE(rtex);
return NULL;
}
@@ -532,27 +531,28 @@ r600_texture_create_object(struct pipe_screen *screen,
* Applies to R600-Cayman. */
rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
- if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
- r600_texture_allocate_fmask(rscreen, rtex);
- r600_texture_allocate_cmask(rscreen, rtex);
- rtex->cmask_buffer = &rtex->resource;
- }
-
- if (!rtex->is_depth && base->nr_samples > 1 &&
- (!rtex->fmask.size || !rtex->cmask.size)) {
- FREE(rtex);
- return NULL;
- }
-
- if (rtex->is_depth &&
- !(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
- R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
- !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
- if (rscreen->chip_class >= SI) {
- /* XXX implement Hyper-Z for SI.
- * Reuse the CMASK allocator, which is almost the same as HTILE. */
- } else {
- r600_texture_allocate_htile(rscreen, rtex);
+ if (rtex->is_depth) {
+ if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
+ R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
+ !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
+ if (rscreen->chip_class >= SI) {
+ /* XXX implement Hyper-Z for SI.
+ * Reuse the CMASK allocator, which is almost the same as HTILE. */
+ } else {
+ r600_texture_allocate_htile(rscreen, rtex);
+ }
+ }
+ } else {
+ if (base->nr_samples > 1) {
+ if (!buf) {
+ r600_texture_allocate_fmask(rscreen, rtex);
+ r600_texture_allocate_cmask(rscreen, rtex);
+ rtex->cmask_buffer = &rtex->resource;
+ }
+ if (!rtex->fmask.size || !rtex->cmask.size) {
+ FREE(rtex);
+ return NULL;
+ }
}
}
--
1.8.3.2
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