[Mesa-dev] [PATCH 04/10] i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.

[Daniel Vetter]

On Thu, Dec 12, 2013 at 01:26:36AM -0800, Kenneth Graunke wrote:
> The PIPE_CONTROL packet actually has 5 DWords on Gen6+:
> 1. Header
> 2. Flags
> 3. Address
> 4. Immediate Data: Lower DWord
> 5. Immediate Data: Upper DWord
> 
> We just never emitted the last one.  While it appears to work, it's
> probably safer to emit the entire thing.

Afaik PIPE_CONTROL auto-switches the size of the write depending upon the
cmd length. We've already seen an increase from gen5 to gen6 (the flags
dword was added) and got away with it in the kernel for an awful lot of
time. So if you don't have any special plans wrt bdw compatibility I don't
think you need this.

MI_FLUSH_DW for the blitter (and other !render rings) works the same
magic. And judging from Bspec that's still the case for bdw+

Cheers, Daniel
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index d2f0e90..bc381fb 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -484,11 +484,12 @@ void
>  brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
>  {
>     if (brw->gen >= 6) {
> -      BEGIN_BATCH(4);
> -      OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
> +      BEGIN_BATCH(5);
> +      OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
>        OUT_BATCH(flags);
>        OUT_BATCH(0);
>        OUT_BATCH(0);
> +      OUT_BATCH(0);
>        ADVANCE_BATCH();
>     } else {
>        BEGIN_BATCH(4);
> -- 
> 1.8.4.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch