[Mesa-dev] [PATCH 06/10] i965: Use full-length PIPE_CONTROL packets for workaround writes.

[Daniel Vetter]

On Thu, Dec 12, 2013 at 01:26:38AM -0800, Kenneth Graunke wrote:
> I believe that PIPE_CONTROL uses the length field to decide whether to
> do 32-bit or 64-bit writes.  A length of 4 would do a 32-bit write,
> while a length of 5 would do a 64-bit write.  (I haven't verified this,
> though.)
> 
> For workaround writes, we don't care what value gets written, or how
> much data.  We're only writing something because hardware bugs mandate
> that do so.  So using a 64-bit write should be fine.
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

Note that 64bit writes with PIPE_CONTROL (and MI_FLUSH_DW, too) have a
stern w/a notice on all gen6+ generations that bit5 of the target address
must be cleared. I haven't checked existing users, but these here seem
safe. So

Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++++++++------
>  1 file changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index d360943..afc4850 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -536,12 +536,13 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
>  {
>     assert(brw->gen == 7);
>  
> -   BEGIN_BATCH(4);
> -   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
> +   BEGIN_BATCH(5);
> +   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
>     OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE);
>     OUT_RELOC(brw->batch.workaround_bo,
>  	     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
>     OUT_BATCH(0); /* write data */
> +   OUT_BATCH(0); /* write data */
>     ADVANCE_BATCH();
>  }
>  
> @@ -552,8 +553,8 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
>  void
>  gen7_emit_cs_stall_flush(struct brw_context *brw)
>  {
> -   BEGIN_BATCH(4);
> -   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
> +   BEGIN_BATCH(5);
> +   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
>     /* From p61 of the Ivy Bridge PRM (1.10.4 PIPE_CONTROL Command: DW1[20]
>      * CS Stall):
>      *
> @@ -571,6 +572,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
>     OUT_RELOC(brw->batch.workaround_bo,
>               I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
>     OUT_BATCH(0);
> +   OUT_BATCH(0);
>     ADVANCE_BATCH();
>  }
>  
> @@ -621,13 +623,14 @@ intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
>     brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
>                                 PIPE_CONTROL_STALL_AT_SCOREBOARD);
>  
> -   BEGIN_BATCH(4);
> -   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
> +   BEGIN_BATCH(5);
> +   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
>     OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
>     OUT_RELOC(brw->batch.workaround_bo,
>               I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
>               PIPE_CONTROL_GLOBAL_GTT_WRITE);
>     OUT_BATCH(0); /* write data */
> +   OUT_BATCH(0); /* write data */
>     ADVANCE_BATCH();
>  
>     brw->batch.need_workaround_flush = false;
> -- 
> 1.8.4.4
> 
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch