[Mesa-dev] [PATCH 08/10] i965: Introduce an OUT_RELOC64 macro.

[Daniel Vetter]

On Thu, Dec 12, 2013 at 01:26:40AM -0800, Kenneth Graunke wrote:
> Broadwell uses 48-bit addresses.  The first DWord is the low 32 bits,
> and the second DWord is the high 16 bits.
> 
> Since individual buffers shouldn't be larger than 4GB in size, any
> offsets into those buffers (buffer->offset + delta) should fit in the
> low 32 bits.  So I believe we can simply emit 0 for the high 16-bits,
> and drm_intel_bo_emit_reloc() should patch it up.
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
> index 159f928..128eed9 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
> @@ -178,6 +178,11 @@ void intel_batchbuffer_cached_advance(struct brw_context *brw);
>  				read_domains, write_domain, delta);	\
>  } while (0)
>  
> +/* Handle 48-bit address relocations for Gen8+ */
> +#define OUT_RELOC64(buf, read_domains, write_domain, delta) \
> +   OUT_RELOC(buf, read_domains, write_domain, delta);       \
> +   OUT_BATCH(0);

Please not. The presumed_offset that libdrm uses is 64bits, and you need
to emit the full presumed address (and correctly shifted). Atm the kernel
never gives you a presumed reloc offset with the high bits set so it
doesn't matter. But I'd prefer if we don't need to make this opt-in
behaviour once we enable address spaces with more than 4G.

i-g-t gets away with the cheap hack since we're allowed to break igt.
Let me check ddx and libva whether I've lost this fight already ...
-Daniel
> +
>  #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
>  #define CACHED_BATCH() intel_batchbuffer_cached_advance(brw);
>  
> -- 
> 1.8.4.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch