[Mesa-dev] [PATCH 5/8] i965: Add a new infrastructure for generating Broadwell shader assembly.
Kenneth Graunke
kenneth at whitecape.org
Tue Dec 17 19:23:01 PST 2013
On 12/10/2013 11:25 PM, Kenneth Graunke wrote:
> This replaces the brw_eu_emit.c layer for Broadwell. It will be
> used by both the vector and scalar shader backends.
>
> v2: Port to use the C-based instruction representation.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
> src/mesa/drivers/dri/i965/Makefile.sources | 1 +
> src/mesa/drivers/dri/i965/gen8_generator.cpp | 650 +++++++++++++++++++++++++++
> src/mesa/drivers/dri/i965/gen8_generator.h | 198 ++++++++
> 3 files changed, 849 insertions(+)
> create mode 100644 src/mesa/drivers/dri/i965/gen8_generator.cpp
> create mode 100644 src/mesa/drivers/dri/i965/gen8_generator.h
>
> diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
> index 4c629cc..ade40ed 100644
> --- a/src/mesa/drivers/dri/i965/Makefile.sources
> +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> @@ -140,5 +140,6 @@ i965_FILES = \
> gen7_wm_state.c \
> gen7_wm_surface_state.c \
> gen8_disasm.c \
> + gen8_generator.cpp \
> gen8_instruction.c \
> $()
> diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp b/src/mesa/drivers/dri/i965/gen8_generator.cpp
> new file mode 100644
> index 0000000..555656d
> --- /dev/null
> +++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
> @@ -0,0 +1,650 @@
> +/*
> + * Copyright © 2012 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +/** @file gen8_generator.cpp
> + *
> + * Code generation for Gen8+ hardware, replacing the brw_eu_emit.c layer.
> + */
> +
> +extern "C" {
> +#include "main/compiler.h"
> +#include "main/macros.h"
> +#include "brw_context.h"
> +} /* extern "C" */
> +
> +#include "glsl/ralloc.h"
> +#include "brw_eu.h"
> +#include "brw_reg.h"
> +#include "gen8_generator.h"
> +
> +gen8_generator::gen8_generator(struct brw_context *brw,
> + struct gl_shader_program *shader_prog,
> + struct gl_program *prog,
> + void *mem_ctx)
> + : shader_prog(shader_prog), prog(prog), brw(brw), mem_ctx(mem_ctx)
> +{
> + ctx = &brw->ctx;
> +
> + memset(&default_state, 0, sizeof(default_state));
> + default_state.mask_control = BRW_MASK_ENABLE;
> +
> + store_size = 1024;
> + store = rzalloc_array(mem_ctx, gen8_instruction, store_size);
> + nr_inst = 0;
> + next_inst_offset = 0;
> +
> + /* Set up the control flow stacks. */
> + if_stack_depth = 0;
> + if_stack_array_size = 16;
> + if_stack = rzalloc_array(mem_ctx, int, if_stack_array_size);
> +
> + loop_stack_depth = 0;
> + loop_stack_array_size = 16;
> + loop_stack = rzalloc_array(mem_ctx, int, loop_stack_array_size);
> +}
> +
> +gen8_generator::~gen8_generator()
> +{
> +}
> +
> +gen8_instruction *
> +gen8_generator::next_inst(unsigned opcode)
> +{
> + gen8_instruction *inst;
> +
> + if (nr_inst + 1 > unsigned(store_size)) {
> + store_size <<= 1;
> + store = reralloc(mem_ctx, store, gen8_instruction, store_size);
> + assert(store);
> + }
> +
> + next_inst_offset += 16;
> + inst = &store[nr_inst++];
> +
> + memset(inst, 0, sizeof(gen8_instruction));
> +
> + gen8_set_opcode(inst, opcode);
> + gen8_set_exec_size(inst, default_state.exec_size);
> + gen8_set_access_mode(inst, default_state.access_mode);
> + gen8_set_mask_control(inst, default_state.mask_control);
> + gen8_set_cond_modifier(inst, default_state.conditional_mod);
> + gen8_set_pred_control(inst, default_state.predicate);
> + gen8_set_pred_inv(inst, default_state.predicate_inverse);
> + gen8_set_saturate(inst, default_state.saturate);
> + gen8_set_flag_subreg_nr(inst, default_state.flag_subreg_nr);
> + return inst;
> +}
> +
> +#define ALU1(OP) \
> +gen8_instruction * \
> +gen8_generator::OP(struct brw_reg dst, struct brw_reg src) \
> +{ \
> + gen8_instruction *inst = next_inst(BRW_OPCODE_##OP); \
> + gen8_set_dst(inst, dst); \
> + gen8_set_src0(inst, src); \
> + return inst; \
> +}
> +
> +#define ALU2(OP) \
> +gen8_instruction * \
> +gen8_generator::OP(struct brw_reg dst, struct brw_reg s0, struct brw_reg s1) \
> +{ \
> + gen8_instruction *inst = next_inst(BRW_OPCODE_##OP); \
> + gen8_set_dst(inst, dst); \
> + gen8_set_src0(inst, s0); \
> + gen8_set_src1(inst, s1); \
> + return inst; \
> +}
> +
> +#define ALU3(OP) \
> +gen8_instruction * \
> +gen8_generator::OP(struct brw_reg dst, struct brw_reg s0, \
> + struct brw_reg s1, struct brw_reg s2) \
> +{ \
> + return alu3(BRW_OPCODE_##OP, dst, s0, s1, s2); \
> +}
> +
> +#define ALU3F(OP) \
> +gen8_instruction * \
> +gen8_generator::OP(struct brw_reg dst, struct brw_reg s0, \
> + struct brw_reg s1, struct brw_reg s2) \
> +{ \
> + assert(dst.type == BRW_REGISTER_TYPE_F); \
> + assert(s0.type == BRW_REGISTER_TYPE_F); \
> + assert(s1.type == BRW_REGISTER_TYPE_F); \
> + assert(s2.type == BRW_REGISTER_TYPE_F); \
> + return alu3(BRW_OPCODE_##OP, dst, s0, s1, s2); \
> +}
> +
> +ALU2(ADD)
> +ALU2(AND)
> +ALU2(ASR)
> +ALU3(BFE)
> +ALU2(BFI1)
> +ALU3(BFI2)
> +ALU1(F32TO16)
> +ALU1(F16TO32)
> +ALU1(BFREV)
> +ALU1(CBIT)
> +ALU2(ADDC)
> +ALU2(SUBB)
> +ALU2(DP2)
> +ALU2(DP3)
> +ALU2(DP4)
> +ALU2(DPH)
> +ALU1(FBH)
> +ALU1(FBL)
> +ALU1(FRC)
> +ALU2(LINE)
> +ALU3F(LRP)
> +ALU3F(MAD)
> +ALU2(MUL)
> +ALU1(MOV)
> +ALU1(NOT)
> +ALU2(OR)
> +ALU2(PLN)
> +ALU1(RNDD)
> +ALU1(RNDE)
> +ALU1(RNDZ)
> +ALU2(SEL)
> +ALU2(SHL)
> +ALU2(SHR)
> +ALU2(XOR)
> +
> +gen8_instruction *
> +gen8_generator::CMP(struct brw_reg dst, unsigned conditional,
> + struct brw_reg src0, struct brw_reg src1)
> +{
> + gen8_instruction *inst = next_inst(BRW_OPCODE_CMP);
> + gen8_set_cond_modifier(inst, conditional);
> + gen8_set_dst(inst, dst);
> + gen8_set_src0(inst, src0);
> + gen8_set_src1(inst, src1);
> + return inst;
> +}
> +
Reviewing my own code here...apparently CMP on float sources produces consistent
but completely perplexing results unless the destination type is also F.
One solution would be to alter the visitors to never generate CMP, D, F, F. But
I'd have to edit both visitors. The other alternative is to just override it here,
which is one line of code and guaranteed to work everywhere.
So, I plan to squash in the following patch:
diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp b/src/mesa/drivers/dri/i965/gen8_generator.cpp
index 555656d..3d5c779 100644
--- a/src/mesa/drivers/dri/i965/gen8_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
@@ -177,6 +177,11 @@ gen8_generator::CMP(struct brw_reg dst, unsigned conditional,
{
gen8_instruction *inst = next_inst(BRW_OPCODE_CMP);
gen8_set_cond_modifier(inst, conditional);
+ /* The CMP instruction appears to behave erratically for floating point
+ * sources unless the destination type is also float. Overriding it to
+ * match src0 makes it work in all cases.
+ */
+ dst.type = src0.type;
gen8_set_dst(inst, dst);
gen8_set_src0(inst, src0);
gen8_set_src1(inst, src1);
More information about the mesa-dev
mailing list