[Mesa-dev] Blorp blit compiler to use FS LIR
Topi Pohjolainen
topi.pohjolainen at intel.com
Fri Dec 20 06:38:29 PST 2013
This is a rather long series but I suspect it will be eventually
squashed into fewer patches. The motivation for the work is to
prepare for gen8 blorp support.
Currently the compiler for the blorp blit programs is written to
emit EU-level instructions directly. This is not a big deal at
the time being as blorp is supported only from gen6 onwards meaning
that there are not that many hw-specific choices to be taken. But
as one moves on to gen8 that will not be the case anymore.
The plan is to lift the core of the blit compiler one level higher,
i.e., to emit FS LIR which can be subsequently fed into gen-specific
generator.
This series aims to keep the generated EU-stream exactly the same
as before. In order to increase the confidence that this is really
the case I wrote a series of unit tests. I identified some 20 odd
individual code blocks in the compiler that emit instructions for
some special purpose. Then I started running piglit tests and
hand-picked some dozen cases that together exercised each of the code
blocks in question at least once. I dumped the key used to drive the
compiler along with the original assembly in human readbale format.
Then I simply placed each such pair as its own unit test case.
I had to modify the existing assembly dumping infra a bit in order to
have it in designated files instead of just stdout. Some care had to
be taken to take the dump in correct phase - after jump instruction
patching but before instruction stream compression. I suppose it
could have been done after the compression as well but I thought
safer to do it just after the generator phase instead.
I also spent some time understanding how the execution size is
controlled in the compiler (also referred to as compression control).
I grouped instructions needing special care into their own
subroutines which I'm hoping to explain better what is going on when
one switches from direct control to higher level.
Similar treatment was required for combining comparisons and for
conditional assignments (predicate control).
Message sending itself (texture fetch, render target write) is going
to be different in gen8 but the message contents look to be more or
less the same. Hence I chose to keep the message building in place
and let the generators to handle only the issuing of the send
command itself.
Finally about the split in general. There is clearly the possibility
of doing all the logic replacement in the compiler core itself
instead of the split. However, that will need to be done more or less
in one go and I thought that the split makes it clearer at least for
initial review what sort of things are involved making it easier to
discuss about the changes.
I'll run tests on SNB also once I get my hands on one.
Topi Pohjolainen (42):
i965/fs: generate fs programs also without any 8-width instructions
i965/fs: allow fs-generator use without gl_fragment_program
i965: dump the disassembly to the given file
i965/blorp: allow unit tests to compile and dump assembly
i965/blorp: unit test compiling blend and scaled
i965/blorp: unit test compiling msaa-8 ums to cms
i965/blorp: unit test compiling msaa-8 cms to cms
i965/blorp: unit test compiling msaa-4 ums to cms
i965/blorp: unit test compiling msaa-8 cms alpha blend
i965/blorp: unit test compiling unaligned msaa-8
i965/blorp: unit test compiling simple zero-src sampled
i965/blorp: unit test compiling bilinear filtered
i965/blorp: unit test compiling gen6 msaa-8 cms alpha blend
i965/blorp: unit test compiling simple gen6 zero-src sampled
i965/blorp: unit test compiling integer typed texture fetches
i965/blorp: remove dependency to compression control state
i965/blorp: reduce the scope of the explicit compression control
i965/blorp: introduce separate eu-emitter for blit compiler
i965/blorp: move emission of pixel kill into eu-emitter
i965: rename tex_ms to tex_cms
i965/fs: introduce non-compressed equivalent of tex_cms
i965/blorp: move emission of texture lookup into eu-emitter
i965/blorp: move emission of rt-write into eu-emitter
i965/blorp: move emission of sample combining into eu-emitter
i965/blorp: wrap emission of conditional assignment
i965/blorp: wrap emission of if-equal-assignment
i965/blorp: wrap LRP
i965/blorp: wrap MOV (/brw_MOV(&func, /emit_mov(/)
i965/blorp: wrap AND (/brw_AND(&func, /emit_and(/)
i965/blorp: wrap ADD (/brw_ADD(&func, /emit_add(/)
i965/blorp: wrap SHR (/brw_SHR(&func, /emit_shr(/)
i965/blorp: wrap SHL (/brw_SHL(&func, /emit_shl(/)
i965/blorp: wrap OR (/brw_OR(&func, /emit_or(/)
i965/blorp: wrap MUL (/brw_MUL(&func, /emit_mul(/)
i965/blorp: wrap FRC (/brw_FRC(&func, /emit_frc(/)
i965/blorp: wrap RNDD (/brw_RNDD(&func, /emit_rndd(/)
i965/blorp: wrap brw_IF/ELSE/ENDIF() into eu-emitter
i965/fs: allow unit tests to dump the final patched assembly
i965/fs: introduce blorp specific rt-write for fs_generator
i965/fs: add support for BRW_OPCODE_AVG in fs_generator
i965/eu: introduce blorp specific flavour of lrp
i965/blorp: switch eu-emitter to use FS IR and fs_generator
src/mesa/drivers/dri/i965/.gitignore | 1 +
src/mesa/drivers/dri/i965/Makefile.am | 8 +-
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 535 ++++------
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 138 +++
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 190 ++++
src/mesa/drivers/dri/i965/brw_defines.h | 4 +-
src/mesa/drivers/dri/i965/brw_eu.c | 20 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.h | 10 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 67 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 +-
src/mesa/drivers/dri/i965/brw_shader.cpp | 11 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 4 +-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 +-
.../drivers/dri/i965/test_blorp_blit_eu_gen.cpp | 1092 ++++++++++++++++++++
17 files changed, 1738 insertions(+), 353 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
create mode 100644 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
create mode 100644 src/mesa/drivers/dri/i965/test_blorp_blit_eu_gen.cpp
--
1.8.3.1
More information about the mesa-dev
mailing list