[Mesa-dev] [PATCH 27/42] i965/blorp: wrap LRP

[Topi Pohjolainen]

The split of the emission of the two halfs into single emission
call prapares for fs_generator support that already does similar
thing. No regressions seen on IVB (unit tests and piglit quick).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  | 26 ++++++++++----------------
 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 13 +++++++++++++
 2 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 1b7310b..b95104e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1679,29 +1679,23 @@ brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples)
    }
 
 #define SAMPLE(x, y) offset(texture_data[x], y)
-   brw_set_access_mode(&func, BRW_ALIGN_16);
-   brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
    for (int index = 3; index > 0; ) {
       /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
        * Counter value of 8 in 'for' loop below is used to interpolate all
        * the color components.
        */
-      for (int k = 0; k < 8; ++k)
-         brw_LRP(&func,
-                 vec8(SAMPLE(index - 1, k)),
-                 offset(x_frac, k & 1),
-                 SAMPLE(index, k),
-                 SAMPLE(index - 1, k));
+      for (int k = 0; k < 8; k += 2)
+         emit_lrp(vec8(SAMPLE(index - 1, k)),
+                  offset(x_frac, k & 1),
+                  SAMPLE(index, k),
+                  SAMPLE(index - 1, k));
       index -= 2;
    }
-   for (int k = 0; k < 8; ++k)
-      brw_LRP(&func,
-              vec8(SAMPLE(0, k)),
-              offset(y_frac, k & 1),
-              vec8(SAMPLE(2, k)),
-              vec8(SAMPLE(0, k)));
-   brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
-   brw_set_access_mode(&func, BRW_ALIGN_1);
+   for (int k = 0; k < 8; k += 2)
+      emit_lrp(vec8(SAMPLE(0, k)),
+               offset(y_frac, k & 1),
+               vec8(SAMPLE(2, k)),
+               vec8(SAMPLE(0, k)));
 #undef SAMPLE
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index 1a023fc..4a7a772 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -74,6 +74,19 @@ protected:
       emit_cond_mov(x, brw_imm_d(y), BRW_CONDITIONAL_EQ, dst, brw_imm_d(src));
    }
 
+   inline void emit_lrp(const struct brw_reg &dst,
+                        const struct brw_reg &src1,
+                        const struct brw_reg &src2,
+                        const struct brw_reg &src3)
+   {
+      brw_set_access_mode(&func, BRW_ALIGN_16);
+      brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
+      brw_LRP(&func, dst, src1, src2, src3);
+      brw_LRP(&func, sechalf(dst), sechalf(src1), sechalf(src2), sechalf(src3));
+      brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
+      brw_set_access_mode(&func, BRW_ALIGN_1);
+   }
+
    void *mem_ctx;
    struct brw_compile func;
 };
-- 
1.8.3.1