[Mesa-dev] [PATCH 0/3] structurizer bugfixes
deathsimple at vodafone.de
Sun Feb 3 05:20:20 PST 2013
Am 01.02.2013 23:58, schrieb Tom Stellard:
> On Fri, Feb 01, 2013 at 04:05:51PM +0100, Christian König wrote:
>> Hi guys,
>> I needed to rearrange the order of patches in this patchset, cause fixing one
>> bug lead to the discovery of a couple of other more nasty bugs.
>> It now fixes four piglit tests with radeonsi and also survives the use cases
>> Tom provided without causing any regression.
>> So please test again, and apply if it now works correctly.
> Hi Christian,
> I've discovered another potential problem, this time with the piglit test:
> ext_timer_query-time-elapsed timestamp
> What's happening is that the EndCF instructions are being reordered within their
> basic block during instruction selection, so if there is an llvm IR block like this:
> ENDIF39: ; preds = %IF40, %ENDIF36
> %temp.2 = phi float [ %77, %IF40 ], [ %58, %ENDIF36 ]
> call void @llvm.R600.endcf(i1 %68)
> %78 = bitcast float %temp4.0 to i32
> %79 = add i32 %78, 1
> %80 = bitcast i32 %79 to float
> br label %Flow
> It is being emitted, like this:
> BB#8: derived from LLVM BB %ENDIF39
> Predecessors according to CFG: BB#6 BB#7
> %vreg14<def> = PHI %vreg11, <BB#6>, %vreg13, <BB#7>; R600_Reg32:%vreg14,%vreg11,%vreg13
> %vreg15<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, -1, %ONE_INT, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg15,%vreg0
> BRANCH <BB#5>
> I've attached the output of the test I mentioned above. It contains the LLVM
> IR before and after the CFG structurizer pass, the SelectionDAG debug optput for
> the problem block and then the resulting MachineInstrs.
I stumbled over the same problem on SI and found a pragmatic two part
First don't set "isBranch" and "isTerminator" for the R600_ENDIF pseudo
instruction, cause otherwise they are grouped at the end of the machine
basic block while emitting them.
And second: Even if you cleaned up the "isBranch" and "isTerminator"
flags it's possible that a PHI node ends up before the ENDIF
instruction, so to avoid problems I just emitted the "S_OR_B64 EXEC,
%reg" instruction at the beginning of the block while lowering the
SI_ENDIF pseudo instruction, instead of the original position.
This approach seems to work fine (at least for SI).
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