[Mesa-dev] [PATCH 10/12] R600/SI: cleanup literal handling v2

[Michel Dänzer]

On Don, 2013-02-14 at 11:43 +0100, Christian König wrote: 
> From: Christian König <christian.koenig at amd.com>
> 
> Seems to be allot simpler, and also paves the
> way for further improvements.
> 
> v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
>     use VGPR0 in dummy EXP, avoid compiler warning, break
>     after encoding the first literal.

Not sure how much this differs from what you wanted to send, but FWIW:


> +    // Only one literal allowed
> +    break;

The same literal could be used for several operands though. :)


> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index ceab692..d62bdd1 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -77,8 +77,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
>      BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
>             .addOperand(MI->getOperand(0))
>             .addOperand(MI->getOperand(1))
> -           .addReg(AMDGPU::SREG_LIT_0)
> -           .addReg(AMDGPU::SREG_LIT_0)
> +           .addImm(0) // SRC1
> +           .addImm(0) // SRC2
>             .addImm(0) // ABS
>             .addImm(1) // CLAMP
>             .addImm(0) // OMOD

For me this resulted in encoding 0 directly (because these operands are
not declared as VSrc_32), i.e. VGPR0, which is no good here.
addImm(0x80) for inline constant 0 worked for me.


-- 
Earthling Michel Dänzer           |                   http://www.amd.com
Libre software enthusiast         |          Debian, X and DRI developer