[Mesa-dev] [PATCH 2/2] R600: Support for TBO

[Tom Stellard]

On Thu, Feb 14, 2013 at 05:47:12PM +0100, Vincent Lejeune wrote:

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

> NOTE: This is a candidate for the Mesa stable branch.
> ---
>  lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp |  3 +-
>  lib/Target/R600/R600Instructions.td                | 54 ++++++++++++++++++++++
>  lib/Target/R600/R600Intrinsics.td                  |  2 +
>  3 files changed, 58 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> index e061b18..7ec783f 100644
> --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> @@ -165,7 +165,8 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
>      case AMDGPU::VTX_READ_GLOBAL_8_eg:
>      case AMDGPU::VTX_READ_GLOBAL_32_eg:
>      case AMDGPU::VTX_READ_GLOBAL_128_eg:
> -    case AMDGPU::TEX_VTX_CONSTBUF: {
> +    case AMDGPU::TEX_VTX_CONSTBUF:
> +    case AMDGPU::TEX_VTX_TEXBUF : {
>        uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
>        uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
>  
> diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
> index 529a4ed..e7efd0b 100644
> --- a/lib/Target/R600/R600Instructions.td
> +++ b/lib/Target/R600/R600Instructions.td
> @@ -1710,6 +1710,60 @@ def TEX_VTX_CONSTBUF :
>  // Inst{127-96} = 0;
>  }
>  
> +def TEX_VTX_TEXBUF:
> +  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
> +      [(set R600_Reg128:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
> +VTX_WORD1_GPR, VTX_WORD0 {
> +
> +let VC_INST = 0;
> +let FETCH_TYPE = 2;
> +let FETCH_WHOLE_QUAD = 0;
> +let SRC_REL = 0;
> +let SRC_SEL_X = 0;
> +let DST_REL = 0;
> +let USE_CONST_FIELDS = 1;
> +let NUM_FORMAT_ALL = 0;
> +let FORMAT_COMP_ALL = 0;
> +let SRF_MODE_ALL = 1;
> +let MEGA_FETCH_COUNT = 16;
> +let DST_SEL_X        = 0;
> +let DST_SEL_Y        = 1;
> +let DST_SEL_Z        = 2;
> +let DST_SEL_W        = 3;
> +let DATA_FORMAT      = 0;
> +
> +let Inst{31-0} = Word0;
> +let Inst{63-32} = Word1;
> +
> +// LLVM can only encode 64-bit instructions, so these fields are manually
> +// encoded in R600CodeEmitter
> +//
> +// bits<16> OFFSET;
> +// bits<2>  ENDIAN_SWAP = 0;
> +// bits<1>  CONST_BUF_NO_STRIDE = 0;
> +// bits<1>  MEGA_FETCH = 0;
> +// bits<1>  ALT_CONST = 0;
> +// bits<2>  BUFFER_INDEX_MODE = 0;
> +
> +
> +
> +// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
> +// is done in R600CodeEmitter
> +//
> +// Inst{79-64} = OFFSET;
> +// Inst{81-80} = ENDIAN_SWAP;
> +// Inst{82}    = CONST_BUF_NO_STRIDE;
> +// Inst{83}    = MEGA_FETCH;
> +// Inst{84}    = ALT_CONST;
> +// Inst{86-85} = BUFFER_INDEX_MODE;
> +// Inst{95-86} = 0; Reserved
> +
> +// VTX_WORD3 (Padding)
> +//
> +// Inst{127-96} = 0;
> +}
> +
> +
>  
>  //===--------------------------------------------------------------------===//
>  // Instructions support
> diff --git a/lib/Target/R600/R600Intrinsics.td b/lib/Target/R600/R600Intrinsics.td
> index b5e4f1e..dc8980a 100644
> --- a/lib/Target/R600/R600Intrinsics.td
> +++ b/lib/Target/R600/R600Intrinsics.td
> @@ -16,6 +16,8 @@ let TargetPrefix = "R600", isTarget = 1 in {
>      Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>    def int_R600_interp_input :
>      Intrinsic<[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> +  def int_R600_load_texbuf :
> +    Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
>    def int_R600_store_swizzle :
>      Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
>    def int_R600_store_stream_output :
> -- 
> 1.8.1.2
> 
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