[Mesa-dev] [PATCH 12/14] R600/SI: replace SI_V_CNDLT with a pattern
Christian König
deathsimple at vodafone.de
Wed Feb 20 09:46:58 PST 2013
From: Christian König <christian.koenig at amd.com>
It actually fixes quite a bunch of piglit tests.
This is a candidate for the mesa-stable branch.
Signed-off-by: Christian König <christian.koenig at amd.com>
---
lib/Target/R600/SIISelLowering.cpp | 22 ----------------------
lib/Target/R600/SIISelLowering.h | 2 --
lib/Target/R600/SIInstructions.td | 12 +++++-------
3 files changed, 5 insertions(+), 31 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index 2f304eb..212e3f2 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -81,9 +81,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
case AMDGPU::SI_WQM:
LowerSI_WQM(MI, *BB, I, MRI);
break;
- case AMDGPU::SI_V_CNDLT:
- LowerSI_V_CNDLT(MI, *BB, I, MRI);
- break;
}
return BB;
}
@@ -127,25 +124,6 @@ void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
MI->eraseFromParent();
}
-void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
- MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
- unsigned VCC = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
-
- BuildMI(BB, I, BB.findDebugLoc(I),
- TII->get(AMDGPU::V_CMP_GT_F32_e32),
- VCC)
- .addImm(0)
- .addOperand(MI->getOperand(1));
-
- BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32_e32))
- .addOperand(MI->getOperand(0))
- .addOperand(MI->getOperand(3))
- .addOperand(MI->getOperand(2))
- .addReg(VCC);
-
- MI->eraseFromParent();
-}
-
EVT SITargetLowering::getSetCCResultType(EVT VT) const {
return MVT::i1;
}
diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h
index a8429b7..5d048f8 100644
--- a/lib/Target/R600/SIISelLowering.h
+++ b/lib/Target/R600/SIISelLowering.h
@@ -29,8 +29,6 @@ class SITargetLowering : public AMDGPUTargetLowering {
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
- void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
- MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 7c157e9..c1c7851 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -990,13 +990,6 @@ def LOAD_CONST : AMDGPUShaderInst <
let usesCustomInserter = 1 in {
-def SI_V_CNDLT : InstSI <
- (outs VReg_32:$dst),
- (ins VReg_32:$src0, VReg_32:$src1, VReg_32:$src2),
- "SI_V_CNDLT $dst, $src0, $src1, $src2",
- [(set VReg_32:$dst, (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2))]
->;
-
def SI_INTERP : InstSI <
(outs VReg_32:$dst),
(ins VReg_32:$i, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, SReg_32:$params),
@@ -1086,6 +1079,11 @@ def SI_KILL : InstSI <
} // end IsCodeGenOnly, isPseudo
+def : Pat<
+ (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2),
+ (V_CNDMASK_B32_e64 VReg_32:$src2, VReg_32:$src1, (V_CMP_GT_F32_e64 0, VReg_32:$src0))
+>;
+
def : Pat <
(int_AMDGPU_kilp),
(SI_KILL (V_MOV_B32_e32 0xbf800000))
--
1.7.10.4
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