[Mesa-dev] [PATCH 2/4] R600/SI: Handle VGPR256 in copyPhysReg

[Tom Stellard]

On Fri, Feb 22, 2013 at 05:02:11PM +0100, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
> 
> 
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> ---
>  lib/Target/R600/SIInstrInfo.cpp | 28 +++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
> index 4dfd26e..a8d573f 100644
> --- a/lib/Target/R600/SIInstrInfo.cpp
> +++ b/lib/Target/R600/SIInstrInfo.cpp
> @@ -41,7 +41,33 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
>    // never be necessary.
>    assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
>  
> -  if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
> +  if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
> +    assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
> +	   AMDGPU::SReg_256RegClass.contains(SrcReg));
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub0))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub0), getKillRegState(KillSrc))
> +            .addReg(DestReg, RegState::Define | RegState::Implicit);
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub1))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub1), getKillRegState(KillSrc))
> +            .addReg(DestReg, RegState::Define | RegState::Implicit);
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub2))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub2), getKillRegState(KillSrc))
> +            .addReg(DestReg, RegState::Define | RegState::Implicit);
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub3))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub3), getKillRegState(KillSrc))
> +            .addReg(DestReg, RegState::Define | RegState::Implicit);
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub4))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub4), getKillRegState(KillSrc))
> +            .addReg(DestReg, RegState::Define | RegState::Implicit);
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub5))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub5), getKillRegState(KillSrc))
> +            .addReg(DestReg, RegState::Define | RegState::Implicit);
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub6))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub6), getKillRegState(KillSrc))
> +            .addReg(DestReg, RegState::Define | RegState::Implicit);
> +    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub7))
> +            .addReg(RI.getSubReg(SrcReg, AMDGPU::sub7), getKillRegState(KillSrc));
> +  } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
>      assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
>  	   AMDGPU::SReg_64RegClass.contains(SrcReg));
>      BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub0))
> -- 
> 1.8.1.3
> 
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