[Mesa-dev] [PATCH 07/12] intel: Replace checks for hiz_mt with has_hiz accessors

[Chad Versace]

That is, replace checks like `hiz_mt != NULL` with
`intel_miptree_slice_has_hiz(...)` where appropriate. This is necessary
because a later patch will selectively disable hiz on individual miptree
slices, and therefore `hiz_mt != NULL` will no longer be a valid
indicator.

This produces no behaviorial change because, currently, if a hiz miptree
is present then hiz is enabled for all slices in the tree.

Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp        | 2 +-
 src/mesa/drivers/dri/i965/brw_clear.c          | 2 +-
 src/mesa/drivers/dri/i965/brw_context.h        | 8 ++++++++
 src/mesa/drivers/dri/i965/brw_misc_state.c     | 7 +++----
 src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 8 ++------
 5 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 88a1a82..f889a33 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -186,7 +186,7 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
    x1 = depth.width;
    y1 = depth.height;
 
-   assert(mt->hiz_mt != NULL);
+   assert(intel_miptree_slice_has_hiz(mt, level, layer));
 
    switch (mt->format) {
    case MESA_FORMAT_Z16:       depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 53d8e54..b2acf74 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -112,7 +112,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
    if (intel->gen < 6)
       return false;
 
-   if (!mt->hiz_mt)
+   if (!intel_renderbuffer_has_hiz(depth_irb))
       return false;
 
    /* We only handle full buffer clears -- otherwise you'd have to track whether
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 4d18152..5092294 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1086,6 +1086,14 @@ struct brw_context
    struct {
       struct intel_mipmap_tree *depth_mt;
       struct intel_mipmap_tree *stencil_mt;
+
+      /**
+       * This is set only when hiz is enabled for the attached depthbuffer.
+       * Note that, in some cases, hiz is disabled for the depthbuffer
+       * despite the presence of a hiz miptree (intel_miptree_mt::hiz_mt).
+       *
+       * \see intel_renderbuffer_has_hiz()
+       */
       struct intel_mipmap_tree *hiz_mt;
 
       /* Inter-tile (page-aligned) byte offsets. */
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 862083a..9650987 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -284,10 +284,9 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
       intel_region_get_tile_masks(depth_mt->region,
                                   &tile_mask_x, &tile_mask_y, false);
 
-      struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
-      if (hiz_mt) {
+      if (intel_miptree_slice_has_hiz(depth_mt, depth_level, depth_layer)) {
          uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
-         intel_region_get_tile_masks(hiz_mt->region,
+         intel_region_get_tile_masks(depth_mt->hiz_mt->region,
                                      &hiz_tile_mask_x, &hiz_tile_mask_y, false);
 
          /* Each HiZ row represents 2 rows of pixels */
@@ -527,7 +526,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
                                          depth_irb->draw_x & ~tile_mask_x,
                                          depth_irb->draw_y & ~tile_mask_y,
                                          false);
-      if (depth_mt->hiz_mt) {
+      if (intel_renderbuffer_has_hiz(depth_irb)) {
          brw->depthstencil.hiz_mt = depth_mt->hiz_mt;
          brw->depthstencil.hiz_offset =
             intel_region_get_aligned_offset(depth_mt->region,
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index ee7e94a..0a90de2 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -917,9 +917,7 @@ intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 					  uint32_t level,
 					  uint32_t layer)
 {
-   intel_miptree_check_level_layer(mt, level, layer);
-
-   if (!mt->hiz_mt)
+   if (!intel_miptree_slice_has_hiz(mt, level, layer))
       return;
 
    intel_resolve_map_set(&mt->hiz_map,
@@ -932,9 +930,7 @@ intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
                                             uint32_t level,
                                             uint32_t layer)
 {
-   intel_miptree_check_level_layer(mt, level, layer);
-
-   if (!mt->hiz_mt)
+   if (!intel_miptree_slice_has_hiz(mt, level, layer))
       return;
 
    intel_resolve_map_set(&mt->hiz_map,
-- 
1.8.1.2