[Mesa-dev] [PATCH 4/4] i965: Support GL_FIXED and packed vertex formats natively on Haswell+.

[Eric Anholt]

Kenneth Graunke <kenneth at whitecape.org> writes:
> diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
> index fc57f8a..0a20055 100644
> --- a/src/mesa/drivers/dri/i965/brw_vs.c
> +++ b/src/mesa/drivers/dri/i965/brw_vs.c
> @@ -440,33 +440,38 @@ static void brw_upload_vs_prog(struct brw_context *brw)
>     brw_populate_sampler_prog_key_data(ctx, prog, &key.tex);
>  
>     /* BRW_NEW_VERTICES */
> -   for (i = 0; i < VERT_ATTRIB_MAX; i++) {
> -      if (vp->program.Base.InputsRead & BITFIELD64_BIT(i)) {
> -         uint8_t wa_flags = 0;
> +   if (intel->gen < 8 && !intel->is_haswell) {
> +      /* Prior to Haswell, the hardware can't natively support GL_FIXED or
> +       * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
> +       */
> +      for (i = 0; i < VERT_ATTRIB_MAX; i++) {
> +         if (vp->program.Base.InputsRead & BITFIELD64_BIT(i)) {
> +            uint8_t wa_flags = 0;

Perhaps use:

if (!(vp->program.Base.InputsRead & BITFIELD64_BIT(i)))
        continue;

to avoid extra indenting?

Other than the fact that I haven't actually double-checked the numbers
in the #defines, this series is:

Reviewed-by: Eric Anholt <eric at anholt.net>
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