[Mesa-dev] [PATCH 2/4] intel: Make intel_region's pitch be bytes instead of pixels.
Eric Anholt
eric at anholt.net
Thu Jan 10 16:14:04 PST 2013
We almost never want a stride in pixels -- if you're doing anything with
a stride, you're specifying an offset or incrementing a pointer, and in
both cases you had to multiply by cpp to get the bytes value you wanted.
But worse, on the way to creating a region from a new tiled BO, we
divided by cpp to get pitch in pixels, and for an RGB32 buffer (an
upcoming change) the pitch wouldn't divide exactly, and we'd end up with
a wrong stride in our region.
---
src/mesa/drivers/dri/i915/i830_texstate.c | 2 +-
src/mesa/drivers/dri/i915/i915_texstate.c | 5 ++---
src/mesa/drivers/dri/i915/i915_vtbl.c | 2 +-
src/mesa/drivers/dri/i965/brw_misc_state.c | 6 +++---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 ++--
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 8 +++----
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 8 +++----
src/mesa/drivers/dri/i965/gen7_misc_state.c | 6 +++---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +++---
src/mesa/drivers/dri/intel/intel_blit.c | 8 +++----
src/mesa/drivers/dri/intel/intel_context.c | 2 +-
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 24 +++++++++++----------
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 2 +-
src/mesa/drivers/dri/intel/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/intel/intel_regions.c | 10 ++++-----
src/mesa/drivers/dri/intel/intel_regions.h | 2 +-
src/mesa/drivers/dri/intel/intel_screen.c | 17 ++++++---------
src/mesa/drivers/dri/intel/intel_tex_copy.c | 4 ++--
src/mesa/drivers/dri/intel/intel_tex_image.c | 9 ++++----
src/mesa/drivers/dri/intel/intel_tex_subimage.c | 6 ++----
src/mesa/drivers/dri/intel/intel_tex_validate.c | 10 +++++----
21 files changed, 67 insertions(+), 77 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index 73ab55e6..f186fac 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -150,7 +150,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
drm_intel_bo_reference(intelObj->mt->region->bo);
i830->state.tex_buffer[unit] = intelObj->mt->region->bo;
- pitch = intelObj->mt->region->pitch * intelObj->mt->cpp;
+ pitch = intelObj->mt->region->pitch;
/* XXX: This calculation is probably broken for tiled images with
* a non-page-aligned offset.
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index 94a8e55..2f32869 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -141,7 +141,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
struct intel_texture_object *intelObj = intel_texture_object(tObj);
struct gl_texture_image *firstImage;
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
- GLuint *state = i915->state.Tex[unit], format, pitch;
+ GLuint *state = i915->state.Tex[unit], format;
GLint lodbias, aniso = 0;
GLubyte border[4];
GLfloat maxlod;
@@ -169,7 +169,6 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
format = translate_texture_format(firstImage->TexFormat,
tObj->DepthMode);
- pitch = intelObj->mt->region->pitch * intelObj->mt->cpp;
state[I915_TEXREG_MS3] =
(((firstImage->Height - 1) << MS3_HEIGHT_SHIFT) |
@@ -187,7 +186,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
*/
maxlod = MIN2(sampler->MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
state[I915_TEXREG_MS4] =
- ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) |
+ ((((intelObj->mt->region->pitch / 4) - 1) << MS4_PITCH_SHIFT) |
MS4_CUBE_FACE_ENA_MASK |
(U_FIXED(CLAMP(maxlod, 0.0, 11.0), 2) << MS4_MAX_LOD_SHIFT) |
((firstImage->Depth - 1) << MS4_VOLUME_DEPTH_SHIFT));
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index e78dbc8..91fde55 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -531,7 +531,7 @@ i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
state[1] = buffer_id;
if (region != NULL) {
- state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
+ state[1] |= BUF_3D_PITCH(region->pitch);
if (region->tiling != I915_TILING_NONE) {
state[1] |= BUF_3D_TILED_SURFACE;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index d7724e3..1024c42 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -656,7 +656,7 @@ static void emit_depthbuffer(struct brw_context *brw)
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
- OUT_BATCH(((region->pitch * region->cpp) - 1) |
+ OUT_BATCH((region->pitch - 1) |
(brw_depthbuffer_format(brw) << 18) |
((hiz_mt ? 1 : 0) << 21) | /* separate stencil enable */
((hiz_mt ? 1 : 0) << 22) | /* hiz enable */
@@ -695,7 +695,7 @@ static void emit_depthbuffer(struct brw_context *brw)
if (hiz_mt) {
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
- OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1);
+ OUT_BATCH(hiz_mt->region->pitch - 1);
OUT_RELOC(hiz_mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
brw->depthstencil.hiz_offset);
@@ -719,7 +719,7 @@ static void emit_depthbuffer(struct brw_context *brw)
* The pitch must be set to 2x the value computed based on width, as
* the stencil buffer is stored with two rows interleaved.
*/
- OUT_BATCH(2 * region->pitch * region->cpp - 1);
+ OUT_BATCH(2 * region->pitch - 1);
OUT_RELOC(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
brw->depthstencil.stencil_offset);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a2a875f..233cd9b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -832,7 +832,7 @@ brw_update_texture_surface(struct gl_context *ctx,
surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
(depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
- ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
+ (intelObj->mt->region->pitch - 1) <<
BRW_SURFACE_PITCH_SHIFT);
surf[4] = 0;
@@ -1205,7 +1205,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
- ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
+ (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 13dbd30..eb61898 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -421,7 +421,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
uint32_t tiling = surface->map_stencil_as_y_tiled
? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y
: brw_get_surface_tiling_bits(region->tiling);
- uint32_t pitch_bytes = region->pitch * region->cpp;
+ uint32_t pitch_bytes = region->pitch;
if (surface->map_stencil_as_y_tiled)
pitch_bytes *= 2;
surf[3] = (tiling |
@@ -844,9 +844,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- uint32_t pitch_bytes =
- params->depth.mt->region->pitch * params->depth.mt->region->cpp;
- OUT_BATCH((pitch_bytes - 1) |
+ OUT_BATCH((params->depth.mt->region->pitch - 1) |
params->depth_format << 18 |
1 << 21 | /* separate stencil enable */
1 << 22 | /* hiz enable */
@@ -876,7 +874,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
- OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
+ OUT_BATCH(hiz_region->pitch - 1);
OUT_RELOC(hiz_region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
hiz_offset);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index e30f6ef..21caa0a 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -188,7 +188,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
- uint32_t pitch_bytes = region->pitch * region->cpp;
+ uint32_t pitch_bytes = region->pitch;
if (surface->map_stencil_as_y_tiled)
pitch_bytes *= 2;
surf[3] = pitch_bytes - 1;
@@ -619,9 +619,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- uint32_t pitch_bytes =
- params->depth.mt->region->pitch * params->depth.mt->region->cpp;
- OUT_BATCH((pitch_bytes - 1) |
+ OUT_BATCH((params->depth.mt->region->pitch - 1) |
params->depth_format << 18 |
1 << 22 | /* hiz enable */
1 << 28 | /* depth write */
@@ -648,7 +646,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
- OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
+ OUT_BATCH(hiz_region->pitch - 1);
OUT_RELOC(hiz_region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
hiz_offset);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 75e9179..7e46398 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -83,7 +83,7 @@ static void emit_depthbuffer(struct brw_context *brw)
/* _NEW_DEPTH, _NEW_STENCIL */
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH(((region->pitch * region->cpp) - 1) |
+ OUT_BATCH((region->pitch - 1) |
(brw_depthbuffer_format(brw) << 18) |
((hiz_mt ? 1 : 0) << 22) | /* hiz enable */
((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
@@ -109,7 +109,7 @@ static void emit_depthbuffer(struct brw_context *brw)
} else {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
- OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1);
+ OUT_BATCH(hiz_mt->region->pitch - 1);
OUT_RELOC(hiz_mt->region->bo,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
@@ -143,7 +143,7 @@ static void emit_depthbuffer(struct brw_context *brw)
* indicate that it does.
*/
OUT_BATCH(enabled |
- (2 * stencil_mt->region->pitch * stencil_mt->region->cpp - 1));
+ (2 * stencil_mt->region->pitch - 1));
OUT_RELOC(stencil_mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
brw->depthstencil.stencil_offset);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 13e8ba8..05e9e75 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -112,8 +112,7 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
/* Compute the pitch in units of tiles. To do this we need to divide the
* pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
*/
- unsigned pitch_bytes = mcs_mt->region->pitch * mcs_mt->cpp;
- unsigned pitch_tiles = pitch_bytes / 128;
+ unsigned pitch_tiles = mcs_mt->region->pitch / 128;
/* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
* GPU address of the MCS buffer; the lower 12 bits contain other control
@@ -332,7 +331,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
- ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1);
+ ((intelObj->mt->region->pitch) - 1);
surf[5] = intelObj->_MaxLevel - tObj->BaseLevel; /* mip count */
@@ -529,7 +528,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
surf[2] = SET_FIELD(rb->Width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(rb->Height - 1, GEN7_SURFACE_HEIGHT);
- surf[3] = (region->pitch * region->cpp) - 1;
+ surf[3] = region->pitch - 1;
surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout);
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 9351df7..4b86f0e 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -292,7 +292,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
__FUNCTION__,
- region->bo, (pitch * cpp),
+ region->bo, pitch,
x1, y1, x2 - x1, y2 - y1);
BR13 = 0xf0 << 16;
@@ -316,7 +316,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
pitch /= 4;
}
#endif
- BR13 |= (pitch * cpp);
+ BR13 |= pitch;
if (is_depth_stencil) {
clear_val = clear_depth_value;
@@ -560,7 +560,7 @@ intel_set_teximage_alpha_to_one(struct gl_context *ctx,
DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
__FUNCTION__,
- intel_image->mt->region->bo, (pitch * cpp),
+ intel_image->mt->region->bo, pitch,
x1, y1, x2 - x1, y2 - y1);
BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
@@ -575,7 +575,7 @@ intel_set_teximage_alpha_to_one(struct gl_context *ctx,
pitch /= 4;
}
#endif
- BR13 |= (pitch * cpp);
+ BR13 |= pitch;
/* do space check before going any further */
aper_array[0] = intel->batch.bo;
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index f3f9983..c9917e5 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1022,7 +1022,7 @@ intel_process_dri2_buffer(struct intel_context *intel,
buffer->cpp,
drawable->w,
drawable->h,
- buffer->pitch / buffer->cpp,
+ buffer->pitch,
buffer->name,
buffer_name);
if (!region)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index ad43781..ce03afa 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -720,16 +720,16 @@ intel_miptree_copy_slice(struct intel_context *intel,
DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
_mesa_get_format_name(src_mt->format),
- src_mt, src_x, src_y, src_mt->region->pitch * src_mt->region->cpp,
+ src_mt, src_x, src_y, src_mt->region->pitch,
_mesa_get_format_name(dst_mt->format),
- dst_mt, dst_x, dst_y, dst_mt->region->pitch * dst_mt->region->cpp,
+ dst_mt, dst_x, dst_y, dst_mt->region->pitch,
width, height);
if (!intelEmitCopyBlit(intel,
dst_mt->region->cpp,
- src_mt->region->pitch * src_mt->region->cpp, src_mt->region->bo,
+ src_mt->region->pitch, src_mt->region->bo,
0, src_mt->region->tiling,
- dst_mt->region->pitch * dst_mt->region->cpp, dst_mt->region->bo,
+ dst_mt->region->pitch, dst_mt->region->bo,
0, dst_mt->region->tiling,
src_x, src_y,
dst_x, dst_y,
@@ -1118,7 +1118,7 @@ intel_miptree_map_gtt(struct intel_context *intel,
x += image_x;
y += image_y;
- map->stride = mt->region->pitch * mt->cpp;
+ map->stride = mt->region->pitch;
map->ptr = base + y * map->stride + x * mt->cpp;
}
@@ -1165,7 +1165,7 @@ intel_miptree_map_blit(struct intel_context *intel,
if (!intelEmitCopyBlit(intel,
mt->region->cpp,
- mt->region->pitch * mt->region->cpp, mt->region->bo,
+ mt->region->pitch, mt->region->bo,
0, mt->region->tiling,
map->stride, map->bo,
0, I915_TILING_NONE,
@@ -1327,15 +1327,15 @@ intel_miptree_unmap_etc(struct intel_context *intel,
image_y += map->y;
uint8_t *dst = intel_region_map(intel, mt->region, map->mode)
- + image_y * mt->region->pitch * mt->region->cpp
+ + image_y * mt->region->pitch
+ image_x * mt->region->cpp;
if (mt->etc_format == MESA_FORMAT_ETC1_RGB8)
- _mesa_etc1_unpack_rgba8888(dst, mt->region->pitch * mt->region->cpp,
+ _mesa_etc1_unpack_rgba8888(dst, mt->region->pitch,
map->ptr, map->stride,
map->w, map->h);
else
- _mesa_unpack_etc2_format(dst, mt->region->pitch * mt->region->cpp,
+ _mesa_unpack_etc2_format(dst, mt->region->pitch,
map->ptr, map->stride,
map->w, map->h, mt->etc_format);
@@ -1394,7 +1394,8 @@ intel_miptree_map_depthstencil(struct intel_context *intel,
map_x + s_image_x,
map_y + s_image_y,
intel->has_swizzling);
- ptrdiff_t z_offset = ((map_y + z_image_y) * z_mt->region->pitch +
+ ptrdiff_t z_offset = ((map_y + z_image_y) *
+ (z_mt->region->pitch / 4) +
(map_x + z_image_x));
uint8_t s = s_map[s_offset];
uint32_t z = z_map[z_offset];
@@ -1453,7 +1454,8 @@ intel_miptree_unmap_depthstencil(struct intel_context *intel,
x + s_image_x + map->x,
y + s_image_y + map->y,
intel->has_swizzling);
- ptrdiff_t z_offset = ((y + z_image_y) * z_mt->region->pitch +
+ ptrdiff_t z_offset = ((y + z_image_y) *
+ (z_mt->region->pitch / 4) +
(x + z_image_x));
if (map_z32f_x24s8) {
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index 6105b42..954dfc5 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -274,7 +274,7 @@ do_blit_bitmap( struct gl_context *ctx,
(GLubyte *)stipple,
sz,
color,
- dst->pitch * dst->cpp,
+ dst->pitch,
dst->bo,
0,
dst->tiling,
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
index 1e524cd..bb9ce99 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -151,7 +151,7 @@ do_blit_readpixels(struct gl_context * ctx,
if (!intelEmitCopyBlit(intel,
src->cpp,
- src->pitch * src->cpp, src->bo, 0, src->tiling,
+ src->pitch, src->bo, 0, src->tiling,
rowLength * src->cpp, dst_buffer, dst_offset, false,
x, y,
dst_x, dst_y,
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index d9e026b..89d91b0 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -210,7 +210,7 @@ intel_region_alloc(struct intel_screen *screen,
return NULL;
region = intel_region_alloc_internal(screen, cpp, width, height,
- aligned_pitch / cpp, tiling, buffer);
+ aligned_pitch, tiling, buffer);
if (region == NULL) {
drm_intel_bo_unreference(buffer);
return NULL;
@@ -344,8 +344,6 @@ _mesa_copy_rect(GLubyte * dst,
{
GLuint i;
- dst_pitch *= cpp;
- src_pitch *= cpp;
dst += dst_x * cpp;
src += src_x * cpp;
dst += dst_y * dst_pitch;
@@ -391,8 +389,8 @@ intel_region_copy(struct intel_context *intel,
return intelEmitCopyBlit(intel,
dst->cpp,
- src_pitch * src->cpp, src->bo, src_offset, src->tiling,
- dst->pitch * dst->cpp, dst->bo, dst_offset, dst->tiling,
+ src_pitch, src->bo, src_offset, src->tiling,
+ dst->pitch, dst->bo, dst_offset, dst->tiling,
srcx, srcy, dstx, dsty, width, height,
logicop);
}
@@ -440,7 +438,7 @@ intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
uint32_t y, bool map_stencil_as_y_tiled)
{
int cpp = region->cpp;
- uint32_t pitch = region->pitch * cpp;
+ uint32_t pitch = region->pitch;
uint32_t tiling = region->tiling;
if (map_stencil_as_y_tiled) {
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h
index 8737a6d..1aff5d9 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.h
+++ b/src/mesa/drivers/dri/intel/intel_regions.h
@@ -63,7 +63,7 @@ struct intel_region
GLuint cpp; /**< bytes per pixel */
GLuint width; /**< in pixels */
GLuint height; /**< in pixels */
- GLuint pitch; /**< in pixels */
+ GLuint pitch; /**< in bytes */
GLubyte *map; /**< only non-NULL when region is actually mapped */
GLuint map_refcount; /**< Reference count for mapping */
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index e0fe8c1..f57db00 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -144,14 +144,14 @@ aub_dump_bmp(struct gl_context *ctx)
continue;
}
+ assert(irb->mt->region->pitch % irb->mt->region->cpp == 0);
drm_intel_gem_bo_aub_dump_bmp(irb->mt->region->bo,
irb->draw_x,
irb->draw_y,
irb->Base.Base.Width,
irb->Base.Base.Height,
format,
- irb->mt->region->pitch *
- irb->mt->region->cpp,
+ irb->mt->region->pitch,
0);
}
}
@@ -413,7 +413,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
{
switch (attrib) {
case __DRI_IMAGE_ATTRIB_STRIDE:
- *value = image->region->pitch * image->region->cpp;
+ *value = image->region->pitch;
return true;
case __DRI_IMAGE_ATTRIB_HANDLE:
*value = image->region->bo->handle;
@@ -522,7 +522,7 @@ intel_create_image_from_names(__DRIscreen *screen,
static __DRIimage *
intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
{
- int width, height, offset, stride, dri_format, cpp, index, pitch;
+ int width, height, offset, stride, dri_format, index;
struct intel_image_format *f;
uint32_t mask_x, mask_y;
__DRIimage *image;
@@ -543,9 +543,7 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
stride = parent->strides[index];
image = intel_allocate_image(dri_format, loaderPrivate);
- cpp = _mesa_get_format_bytes(image->format); /* safe since no none format */
- pitch = stride / cpp;
- if (offset + height * cpp * pitch > parent->region->bo->size) {
+ if (offset + height * stride > parent->region->bo->size) {
_mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
free(image);
return NULL;
@@ -560,7 +558,7 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
image->region->cpp = _mesa_get_format_bytes(image->format);
image->region->width = width;
image->region->height = height;
- image->region->pitch = pitch;
+ image->region->pitch = stride;
image->region->refcount = 1;
image->region->bo = parent->region->bo;
drm_intel_bo_reference(image->region->bo);
@@ -1174,8 +1172,7 @@ intelAllocateBuffer(__DRIscreen *screen,
intelBuffer->base.attachment = attachment;
intelBuffer->base.cpp = intelBuffer->region->cpp;
- intelBuffer->base.pitch =
- intelBuffer->region->pitch * intelBuffer->region->cpp;
+ intelBuffer->base.pitch = intelBuffer->region->pitch;
return &intelBuffer->base;
}
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 47b8dc3..1af7b1c 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -125,11 +125,11 @@ intel_copy_texsubimage(struct intel_context *intel,
/* blit from src buffer to texture */
if (!intelEmitCopyBlit(intel,
intelImage->mt->cpp,
- src_pitch * region->cpp,
+ src_pitch,
region->bo,
0,
region->tiling,
- intelImage->mt->region->pitch * intelImage->mt->cpp,
+ intelImage->mt->region->pitch,
intelImage->mt->region->bo,
0,
intelImage->mt->region->tiling,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 387f5a5..8e5b4b4 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -139,7 +139,7 @@ try_pbo_upload(struct gl_context *ctx,
struct intel_context *intel = intel_context(ctx);
struct intel_buffer_object *pbo = intel_buffer_object(unpack->BufferObj);
GLuint src_offset, src_stride;
- GLuint dst_x, dst_y, dst_stride;
+ GLuint dst_x, dst_y;
drm_intel_bo *dst_buffer, *src_buffer;
if (!_mesa_is_bufferobj(unpack->BufferObj))
@@ -188,13 +188,11 @@ try_pbo_upload(struct gl_context *ctx,
intelImage->base.Base.Face,
&dst_x, &dst_y);
- dst_stride = intelImage->mt->region->pitch * intelImage->mt->region->cpp;
-
if (!intelEmitCopyBlit(intel,
intelImage->mt->cpp,
src_stride, src_buffer,
src_offset, false,
- dst_stride, dst_buffer, 0,
+ intelImage->mt->region->pitch, dst_buffer, 0,
intelImage->mt->region->tiling,
0, 0, dst_x, dst_y, image->Width, image->Height,
GL_COPY)) {
@@ -278,7 +276,8 @@ intel_set_texture_image_region(struct gl_context *ctx,
intel_texobj->needs_validate = true;
intel_image->mt->offset = offset;
- intel_image->base.RowStride = region->pitch;
+ assert(region->pitch % region->cpp == 0);
+ intel_image->base.RowStride = region->pitch / region->cpp;
/* Immediately validate the image to the object. */
intel_miptree_reference(&intel_texobj->mt, intel_image->mt);
diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
index bf9d2dc..7a2f713 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
@@ -129,8 +129,6 @@ intel_blit_texsubimage(struct gl_context * ctx,
}
bool ret;
- unsigned int dst_pitch = intelImage->mt->region->pitch *
- intelImage->mt->cpp;
drm_intel_gem_bo_unmap_gtt(temp_bo);
@@ -138,7 +136,7 @@ intel_blit_texsubimage(struct gl_context * ctx,
intelImage->mt->cpp,
dstRowStride,
temp_bo, 0, false,
- dst_pitch,
+ intelImage->mt->region->pitch,
intelImage->mt->region->bo, 0,
intelImage->mt->region->tiling,
0, 0, blit_x, blit_y, width, height,
@@ -268,7 +266,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
const uint32_t cpp = 4; /* chars per pixel of GL_BGRA */
const uint32_t swizzle_width_pixels = 16;
- const uint32_t stride_bytes = image->mt->region->pitch * cpp;
+ const uint32_t stride_bytes = image->mt->region->pitch;
const uint32_t width_tiles = stride_bytes / tile_width_bytes;
for (uint32_t y_pixels = yoffset; y_pixels < y_max_pixels; ++y_pixels) {
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index c849366..6aaed60 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -172,7 +172,8 @@ intel_tex_map_image_for_swrast(struct intel_context *intel,
*/
for (i = 0; i < mt->level[level].depth; i++) {
intel_miptree_get_image_offset(mt, level, i, &x, &y);
- intel_image->base.ImageOffsets[i] = x + y * mt->region->pitch;
+ intel_image->base.ImageOffsets[i] = x + y * (mt->region->pitch /
+ mt->region->cpp);
}
DBG("%s \n", __FUNCTION__);
@@ -183,13 +184,14 @@ intel_tex_map_image_for_swrast(struct intel_context *intel,
intel_miptree_get_image_offset(mt, level, face, &x, &y);
DBG("%s: (%d,%d) -> (%d, %d)/%d\n",
- __FUNCTION__, face, level, x, y, mt->region->pitch * mt->cpp);
+ __FUNCTION__, face, level, x, y, mt->region->pitch);
intel_image->base.Map = intel_region_map(intel, mt->region, mode) +
- (x + y * mt->region->pitch) * mt->cpp;
+ x * mt->cpp + y * mt->region->pitch;
}
- intel_image->base.RowStride = mt->region->pitch;
+ assert(mt->region->pitch % mt->region->cpp == 0);
+ intel_image->base.RowStride = mt->region->pitch / mt->region->cpp;
}
static void
--
1.7.10.4
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