[Mesa-dev] [PATCH 2/6] radeonsi: Enable tiling for depth/stencil resources.

[Michel Dänzer]

From: Michel Dänzer <michel.daenzer at amd.com>

Enabling it for all resources still seems to cause problems, but depth/stencil
buffers are always accessed with tiling by the DB block.

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
 src/gallium/drivers/radeonsi/r600_texture.c |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c
index de46640..6ea6220 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -521,14 +521,13 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 	unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
 	int r;
 
-#if 0
 	if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
-	    !(templ->bind & PIPE_BIND_SCANOUT)) {
+	    !(templ->bind & PIPE_BIND_SCANOUT) &&
+	    util_format_is_depth_or_stencil(templ->format)) {
 		if (permit_hardware_blit(screen, templ)) {
 			array_mode = V_009910_ARRAY_2D_TILED_THIN1;
 		}
 	}
-#endif
 
 	r = r600_init_surface(rscreen, &surface, templ, array_mode,
 			      templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
-- 
1.7.10.4