[Mesa-dev] [PATCH] intel: Fix ReadPixels on buffers whose width >= 32kbytes

[Ian Romanick]

On 01/24/2013 02:10 PM, Paul Berry wrote:
> When possible, glReadPixels calls are performed using the hardware
> blitter.  However, according to the Ivy Bridge PRM, Vol1 Part4,
> section 1.2.1.2 (Graphics Data Size Limitations):
>
>      The BLT engine is capable of transferring very large quantities of
>      graphics data. Any graphics data read from and written to the
>      destination is permitted to represent a number of pixels that
>      occupies up to 65,536 scan lines and up to 32,768 bytes per scan
>      line at the destination. The maximum number of pixels that may be
>      represented per scan line’s worth of graphics data depends on the
>      color depth.
>
> With an RGBA32F color buffer (which has 16 bytes per pixel) this
> imposes a maximum width of 2048 pixels.
>
> To make matters worse, if the pitch of the buffer is 32k or greater,
> intel_miptree_map_blit's call to intelEmitCopyBlit will overflow
> intelEmitCopyBlit's src_pitch and dst_pitch parameters (which are
> 16-bit signed integers).
>
> We can conveniently avoid both problems by avoiding the readpixels
> blit path when the miptree's pitch is >= 32k.
>
> Fixes gles3conform "half_float" tests when the buffer width is greater
> than 2048.

It also fixes some other other tests a > 4k pixel width, but this commit 
message is fine.

Tested-by: Ian Romanick <ian.d.romanick at intel.com>

> ---
>   src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> index ce03afa..f2571bd 100644
> --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> @@ -1568,7 +1568,8 @@ intel_miptree_map_singlesample(struct intel_context *intel,
>      } else if (intel->has_llc &&
>   	      !(mode & GL_MAP_WRITE_BIT) &&
>   	      !mt->compressed &&
> -	      mt->region->tiling == I915_TILING_X) {
> +	      mt->region->tiling == I915_TILING_X &&
> +              mt->region->pitch < 32768) {
>         intel_miptree_map_blit(intel, mt, map, level, slice);
>      } else {
>         intel_miptree_map_gtt(intel, mt, map, level, slice);
>