[Mesa-dev] [RFC PATCH 06/12] i965: Implement opcodes for the hw-generated binding table EDIT commands

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h     |    5 +++++
 src/mesa/drivers/dri/i965/brw_state.h       |    6 ++++++
 src/mesa/drivers/dri/i965/gen7_misc_state.c |   31 +++++++++++++++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index c990958..81431d0 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1165,6 +1165,11 @@ enum brw_message_target {
 /* Haswell hardware-generated binding tables */
 #define _3DSTATE_BINDING_TABLE_POOL_ALLOC       0x7919 /* GEN7.5+ */
 # define HSW_BINDING_TABLE_ALLOC_OFFSET         0x860  /* GEN7.5+ */
+#define _3DSTATE_BINDING_TABLE_EDIT_VS          0x7843 /* GEN7.5 */
+#define _3DSTATE_BINDING_TABLE_EDIT_GS          0x7844 /* GEN7.5 */
+#define _3DSTATE_BINDING_TABLE_EDIT_HS          0x7845 /* GEN7.5 */
+#define _3DSTATE_BINDING_TABLE_EDIT_DS          0x7846 /* GEN7.5 */
+#define _3DSTATE_BINDING_TABLE_EDIT_PS          0x7847 /* GEN7.5 */
 
 #define _3DSTATE_SAMPLER_STATE_POINTERS		0x7802 /* GEN6+ */
 # define PS_SAMPLER_STATE_CHANGE				(1 << 12)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index eecc1f2..c8808c8 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -216,6 +216,12 @@ get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
 void gen7_rs_control(struct brw_context *brw, int enable);
 void gen7_enable_hw_binding_tables(struct brw_context *brw);
 void gen7_update_hw_bt(struct brw_context *brw);
+void gen7_update_vs_binding_table(struct brw_context *brw,
+                                  uint32_t index,
+                                  uint32_t surf_offset);
+void gen7_update_ps_binding_table(struct brw_context *brw,
+                                  uint32_t index,
+                                  uint32_t surf_offset);
 
 /* gen7_urb.c */
 void gen7_allocate_push_constants(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 11464a2..ae9c485 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -150,6 +150,37 @@ gen7_rs_control(struct brw_context *brw, int enable)
 }
 
 void
+gen7_update_vs_binding_table(struct brw_context *brw,
+                                  uint32_t index,
+                                  uint32_t surf_offset)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(3);
+   OUT_BATCH(_3DSTATE_BINDING_TABLE_EDIT_VS << 16 | (3 - 2));
+   OUT_BATCH(0x3);
+   OUT_BATCH(index << 16 | (surf_offset & 0xFFFFF) >> 5);
+   ADVANCE_BATCH();
+   brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
+}
+
+void
+gen7_update_ps_binding_table(struct brw_context *brw,
+                                  uint32_t index,
+                                  uint32_t surf_offset)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(3);
+   OUT_BATCH(_3DSTATE_BINDING_TABLE_EDIT_PS << 16 | (3 - 2));
+   OUT_BATCH(0x3);
+   OUT_BATCH(index << 16 | (surf_offset & 0xFFFFF) >> 5);
+   ADVANCE_BATCH();
+
+   brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
+}
+
+void
 gen7_enable_hw_binding_tables(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
-- 
1.7.9.5