[Mesa-dev] [RFC PATCH 11/12] i965/blorp: In blorp, update PS on-chip binding table when new surface state entries are generated

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/gen6_blorp.cpp |   16 +++++++++++++++-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |    3 ++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d900734..a88148e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -459,8 +459,22 @@ gen6_blorp_emit_binding_table(struct brw_context *brw,
                               uint32_t wm_surf_offset_renderbuffer,
                               uint32_t wm_surf_offset_texture)
 {
+   struct intel_context *intel = &brw->intel;
    uint32_t wm_bind_bo_offset;
-   uint32_t *bind = (uint32_t *)
+   uint32_t *bind;
+
+   if (intel->is_haswell) {
+      gen7_update_ps_binding_table(brw,
+                                     BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
+                                     wm_surf_offset_renderbuffer);
+      gen7_update_ps_binding_table(brw,
+                                     BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
+                                     wm_surf_offset_texture);
+
+      return brw->wm.bind_bo_offset;
+   }
+
+   bind = (uint32_t *)
       brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
                       sizeof(uint32_t) *
                       BRW_BLORP_NUM_BINDING_TABLE_ENTRIES,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 822f954..4ec95e2 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -156,7 +156,8 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
       ? I915_TILING_Y : region->tiling;
 
    uint32_t *surf = (uint32_t *)
-      brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
+      brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4,
+                      intel->is_haswell? 64 : 32, &wm_surf_offset);
    memset(surf, 0, 8 * 4);
 
    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
-- 
1.7.9.5