[Mesa-dev] [PATCH 05/13] i965: Delete "the data cache is the sampler cache" comments on Gen7+.

[Daniel Vetter]

On Wed, Jul 10, 2013 at 04:27:59PM -0700, Kenneth Graunke wrote:
> I cut and pasted these comments from the Gen4 code during Ivybridge
> enabling, and didn't understand what they meant at the time.
> 
> The data cache is NOT the same as the sampler cache on Ivybridge.
> The sampler cache has L1 and L2 caches in addition to the L3 cache,
> while data port messages to the "data cache" hit L3 directly.
> 
> This means that the sampler domain is technically wrong, but we stopped
> caring about read/write domains quite a while ago.  The kernel just
> flushes all the caches at the end of each batchbuffer, and our render to
> texture code flushes the sampler caches when necessary.

Just a quick clarification here: The kernel stopped caring about the
domain you put in a while ago (if it's not one of the special ones that
e.g. trigger a wa on gen6). We still very much care about read vs. write
domains to optimize cpu readbacks to only stall for the last write, not
the last read. Unfortunately the gtt mmap interface exposed by libdrm
doesn't allow drivers to specify this, but for cpu mmaps it goes through.
And SNA with it's kgem fully exploits it ofc.
-Daniel

> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 12 ------------
>  1 file changed, 12 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> index 8c54152..684669b 100644
> --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> @@ -259,10 +259,6 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx,
>     if (bo) {
>        surf[1] = bo->offset; /* reloc */
>  
> -      /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
> -       * bspec ("Data Cache") says that the data cache does not exist as
> -       * a separate cache and is just the sampler cache.
> -       */
>        drm_intel_bo_emit_reloc(brw->batch.bo,
>  			      binding_table[surf_index] + 4,
>  			      bo, 0,
> @@ -414,10 +410,6 @@ gen7_create_constant_surface(struct brw_context *brw,
>                  SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
>     }
>  
> -   /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
> -    * bspec ("Data Cache") says that the data cache does not exist as
> -    * a separate cache and is just the sampler cache.
> -    */
>     drm_intel_bo_emit_reloc(brw->batch.bo,
>  			   *out_offset + 4,
>  			   bo, offset,
> @@ -454,10 +446,6 @@ gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
>      * overrides.
>      */
>  
> -   /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
> -    * bspec ("Data Cache") says that the data cache does not exist as
> -    * a separate cache and is just the sampler cache.
> -    */
>     drm_intel_bo_emit_reloc(brw->batch.bo,
>                             *out_offset + 4,
>                             brw->shader_time.bo, 0,
> -- 
> 1.8.3.2
> 
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> mesa-dev at lists.freedesktop.org
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch