[Mesa-dev] [PATCH] i965: allow 8 user clip planes on CTG+

[Kenneth Graunke]

On 07/14/2013 02:43 AM, Chris Forbes wrote:
> There's no reason to restrict to 6 planes on CTG and ILK -- no bugs to
> work around which require the top clip flag.

Right, there's no negative RHW bug to work around using a slot...so I 
agree this should be doable.  And also necessary for 1.30.

I'm a little paranoid that there might be some hardcoded limits in the 
clipping code (arrays not big enough, loops that don't go all the way, 
etc...).

I've been looking through the code for the magic number 6, and it 
appears an awful lot of places...though often as 6 + nr_userclip + 1, 
which sounds like the 6 bounds of the view volume, so I think we're okay 
there.

In brw_clip.h, there's a #define MAX_VERTS (3+6+6) (with no comments 
what those are for - eesh)...does one of those need to be an 8?

I agree with this patch in principle, though, and am not up to speed on 
the details, so if you take a look and still think everything is fine:
Acked-by: Kenneth Graunke <kenneth at whitecape.org>

> This is another tiny step toward GLSL 1.30 support.
>
> Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
> ---
>   src/mesa/drivers/dri/i965/brw_clip_tri.c | 4 ++--
>   src/mesa/drivers/dri/i965/brw_context.c  | 2 +-
>   2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
> index bea0853..61d613e 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
> @@ -273,9 +273,9 @@ void brw_clip_tri( struct brw_clip_compile *c )
>      brw_MOV(p, get_addr_reg(freelist_ptr), brw_address(c->reg.vertex[3]) );
>
>      /* Set the initial vertex source mask: The first 6 planes are the bounds
> -    * of the view volume; the next 6 planes are the user clipping planes.
> +    * of the view volume; the next 8 planes are the user clipping planes.
>       */
> -   brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0xfc0));
> +   brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0x3fc0));
>
>      brw_DO(p, BRW_EXECUTE_1);
>      {
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index a72e226..accbe2d 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -190,7 +190,7 @@ brw_initialize_context_constants(struct brw_context *brw)
>      ctx->Const.MaxPointSizeAA = 255.0;
>      ctx->Const.PointSizeGranularity = 1.0;
>
> -   if (brw->gen >= 6)
> +   if (brw->gen >= 5 || brw->is_g4x)
>         ctx->Const.MaxClipPlanes = 8;
>
>      ctx->Const.VertexProgram.MaxNativeInstructions = 16 * 1024;
>