[Mesa-dev] [PATCH 2/2] i965/hsw: Set MOCS to L3_CACHEABLE for some packets

[Chris Wilson]

On Wed, Jul 17, 2013 at 02:28:55PM -0700, Chad Versace wrote:
> Set MOCS to L3_CACHEABLE for the following packets, during the normal
> draw upload path and during blorp:
>     SURFACE_STATE
>     3DSTATE_DEPTH_BUFFER
>     3DSTATE_HIER_DEPTH_BUFFER
>     3DSTATE_STENCIL_BUFFER
> 
> It's not possible to set the MOCS of the MCS buffer, because the MCS
> inherits MOCS from the parent surface.
> 
> Performance Measurements
> ========================
> 
> system-info {
>     gpu: haswell_m_gt2 0x0416 rev05
>     arch: x86_64
>     kernel: 3.9.9-1-ARCH (Archlinux)
>     xf86-video-intel: 2.12.11-1 (Archlinux)
>     libdrm: 2.4.46-2 (Archlinux)
> }
> 
> test {
>     name: pts/xonotic-1.3.1 1920x1080 quality=high
>     n: 3
>     delta: +3.827% +/- 1.55968% (student's t) at 95% confidence
>     pooled-s: 0.322153
>     mesa-base: master-00d32cd
> }
> 
> CC: Kenneth Graunke <kenneth at whitecape.org>
> Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
> ---
>  src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 19 +++++++++++++++++--
>  src/mesa/drivers/dri/i965/gen7_misc_state.c       | 13 +++++++++++--
>  src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 18 +++++++++++++++++-
>  3 files changed, 45 insertions(+), 5 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> index fbdd2be..b85756d 100644
> --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> @@ -143,6 +143,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
>      */
>     struct intel_region *region = surface->mt->region;
>     uint32_t tile_x, tile_y;
> +   uint32_t mocs;
>  
>     uint32_t tiling = surface->map_stencil_as_y_tiled
>        ? I915_TILING_Y : region->tiling;
> @@ -151,6 +152,12 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
>        brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
>     memset(surf, 0, 8 * 4);
>  
> +   if (brw->is_haswell) {
> +      mocs = HSW_MOCS_L3_CACHEABLE;
> +   } else {
> +      mocs = 0;
> +   }

Do you not have to worry about scanout coherency (e.g. frontbuffer
rendering)?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre