[Mesa-dev] [PATCH 0/2] i965/hsw: Use MOCS to cache stuff in L3

[Chad Versace]

NAK this. Better perf changes coming in v2.

On 07/17/2013 02:28 PM, Chad Versace wrote:
> Performance Measurements
> ========================
>
> test {
>      name: pts/xonotic-1.3.1 1920x1080 quality=high
>      n: 3
>      delta: +3.827% +/- 1.55968% (student's t) at 95% confidence
>      pooled-s: 0.322153
>      mesa-base: master-00d32cd
> }
>
>
> system-info {
>      gpu: haswell_m_gt2 0x0416 rev05
>      arch: x86_64
>      kernel: 3.9.9-1-ARCH (Archlinux)
>      xf86-video-intel: 2.12.11-1 (Archlinux)
>      libdrm: 2.4.46-2 (Archlinux)
> }
>
> Chad Versace (2):
>    i965/gen7: Add defines for Memory Object Control State
>    i965/hsw: Set MOCS to L3_CACHEABLE for some packets
>
>   src/mesa/drivers/dri/i965/brw_defines.h           | 20 ++++++++++++++++++++
>   src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 19 +++++++++++++++++--
>   src/mesa/drivers/dri/i965/gen7_misc_state.c       | 13 +++++++++++--
>   src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 18 +++++++++++++++++-
>   4 files changed, 65 insertions(+), 5 deletions(-)
>