[Mesa-dev] [PATCH 1/2] i965/gen7: Add defines for Memory Object Control State

[Chad Versace]

On 07/18/2013 12:20 AM, Kenneth Graunke wrote:
> On 07/17/2013 04:46 PM, Chad Versace wrote:


>> +/* Memory Object Control State, Gen7 */
>> +/* L3 Cacheability Control */
>> +#define GEN7_MOCS_L3_UNCACHEABLE                0
>> +#define GEN7_MOCS_L3_CACHEABLE                  1
>> +/* LCC Cacheability Control */
>> +#define GEN7_MOCS_LCC_USE_PTE                   (0 << 1)
>> +#define GEN7_MOCS_LCC_CACHEABLE                 (1 << 1)
>> +
>> +/* Memory Object Control State, Haswell */
>> +/* L3 Cacheability Control */
>> +#define HSW_MOCS_L3_UNCACHEABLE                 0
>> +#define HSW_MOCS_L3_CACHEABLE                   1
>> +/* LCC Cacheability Control */
>> +#define HSW_MOCS_LCC_USE_PTE                    (0 << 1)
>> +#define HSW_MOCS_LCC_UNCACHEABLE                (1 << 1)
>> +#define HSW_MOCS_LCC_WB_TO_LLC_ELLC             (2 << 1)
>> +#define HSW_MOCS_LCC_WB_TO_ELLC                 (3 << 1)
>> +
>>   #include "intel_chipset.h"
>>
>>   #endif
>
> I'm really not a fan of "LCC", as that isn't a term used in the documentation.  It's "LLC/eLLC Cacheability Control
> (LLCCC)".

I'm not a fan of that LCC either. Glad to see you chose a better naming scheme.

>
> Also, the L3 defines are the same on Ivybridge, Haswell, and Baytrail...so it would be nice to just use GEN7 rather than
> having HSW #defines.

I agree.

>
> Chad, would you be okay with using the names in the patches I just sent out instead of these?  I feel like they're a bit
> more descriptive, and they have GEN7_* for shared code, and platform-specific ones for both Haswell and Baytrail.

I think your naming scheme is better, so let's go with yours. But I do have a comment/request on your names; see the 
reply to your patch.

> Sorry for the trouble...

No trouble. The mailing list is here to make code better, and that's we're doing now.