[Mesa-dev] [PATCH v2 00/13] Enable GL_AMD_vertex_shader_layer extension

[Jordan Justen]

git://people.freedesktop.org/~jljusten/mesa ivb-full-depth-buffer-v2

This series converts DEPTH_BUFFER to use the LOD and
minimum array element fields and always points the
depth, hiz and stencil buffers at the top of the
miptree surface.

This should allows us to support layered rendering,
although testing of this is not completed. Layered
rendering will be required for GL 3.2 / GLSL 1.50
support, but it can also be exposed via the
GL_AMD_vertex_shader_layer extension.

v2:
 * New patch 8
   "gen7 fbo: make unmatched depth/stencil configs return unsupported"
 * Patch 11 is re-written based on code review
   "i965 gen7: don't set FORCE_ZERO_RTAINDEX for layered rendering"
 * New patch 12
   "intel_mipmap_tree: all layers need hiz resolves with layered rendering"
 * Note: all other patches have been reviewed-by Paul

Testing on IVB and HSW:
* Piglit: Fixes array-depth-roundtrip

Testing on IVB:
* AMD_vertex_shader_layer piglit tests on list
* Basic visual inspection of Unigine Tropics
* Brief testing with Portal & DOTA2

Jordan Justen (13):
  i965: init global state first in
    brw_workaround_depthstencil_alignment
  gen7 depth surface: calculate more specific surface type
  gen7 depth surface: calculate depth (array size) for depth surface
  gen7 depth surface: calculate LOD being rendered to
  gen7 depth surface: calculate minimum array element being rendered
  gen7 blorp depth: calculate base surface width/height
  hsw hiz: Add new size restrictions for miplevels > 0
  gen7 fbo: make unmatched depth/stencil configs return unsupported
  gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
  hsw hiz: Remove x/y offset restriction for hiz
  i965 gen7: don't set FORCE_ZERO_RTAINDEX for layered rendering
  intel_mipmap_tree: all layers need hiz resolves with layered
    rendering
  intel: enable GL_AMD_vertex_shader_layer extension for gen7+

 src/mesa/drivers/dri/i965/brw_misc_state.c    |   25 +++++--
 src/mesa/drivers/dri/i965/brw_tex_layout.c    |   10 +--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp      |  100 +++++++++++++------------
 src/mesa/drivers/dri/i965/gen7_clip_state.c   |    2 +-
 src/mesa/drivers/dri/i965/gen7_misc_state.c   |   83 ++++++++++++++++++--
 src/mesa/drivers/dri/i965/intel_extensions.c  |    4 +
 src/mesa/drivers/dri/i965/intel_fbo.c         |   16 ++++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |   61 ++++++++-------
 8 files changed, 203 insertions(+), 98 deletions(-)

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1.7.10.4