[Mesa-dev] [PATCH] i965/vs: Fix flaky texture swizzling

[Kenneth Graunke]

On 07/23/2013 03:26 AM, Chris Forbes wrote:
> If any component used the ZERO or ONE swizzle, its corresponding member
> in the `swizzle` array would never be initialized. We *mostly* got away
> with this, except when that memory happened to contain a value that
> clobbered another channel when combined using BRW_SWIZZLE4().
>
> NOTE: This is a candidate for stable branches.
>
> Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
> ---
>   src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 3eb43a8..1d86b33 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -2506,7 +2506,7 @@ vec4_visitor::swizzle_result(ir_texture *ir, src_reg orig_val, int sampler)
>      }
>
>      int zero_mask = 0, one_mask = 0, copy_mask = 0;
> -   int swizzle[4];
> +   int swizzle[4] = {0};
>
>      for (int i = 0; i < 4; i++) {
>         switch (GET_SWZ(s, i)) {

Oh, yikes!  Good catch...

A bit more verbose explanation:

BRW_SWIZZLE4 is:

    (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))

with no bitmasking, which means that if swizzle[i]'s value doesn't fit 
in 2 bits, it'll clobber the other swizzle channels, breaking things in 
bizarre ways.  It doesn't actually matter what channel we pick, but 
uninitialized values are often more than 2-bits :)

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>