[Mesa-dev] [PATCH] R600: Improve vector constant loading for EG/SI

[Tom Stellard]

On Fri, Jun 21, 2013 at 09:44:29AM -0500, Aaron Watry wrote:
> Add some constant load v2i32/v4i32 tests for both EG and SI.
> 
> Tested on: Pitcairn (7850) and Cedar (54xx)
> 
> Signed-off-by: Aaron Watry <awatry at gmail.com>
> ---
>  lib/Target/R600/R600Instructions.td |  3 +++
>  lib/Target/R600/SIInstructions.td   | 10 ++++++++++
>  test/CodeGen/R600/load.vec.ll       | 27 +++++++++++++++++++++++++++
>  3 files changed, 40 insertions(+)
> 
> diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
> index 803f597..219358c 100644
> --- a/lib/Target/R600/R600Instructions.td
> +++ b/lib/Target/R600/R600Instructions.td
> @@ -1421,6 +1421,9 @@ def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
>    [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
>  >;
>  
> +def CONSTANT_LOAD_128_eg : VTX_READ_128_eg <1,
> +  [(set v4i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
> +>;
>  

It would be nice if you could add the equivalent instruction for Cayman
too.

>  } // End Predicates = [isEG]
>  
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 9c96c08..0058c0d 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -1629,6 +1629,16 @@ multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
>    >;
>  
>    def : Pat <
> +    (vt (constant_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
> +    (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
> +  >;
> +
> +  def : Pat <
> +    (vt (constant_ld i64:$ptr)),
> +    (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
> +  >;
> +
> +  def : Pat <
>       (vt (constant_ld (add i64:$ptr, i64:$offset))),
>       (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
>    >;
> diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll
> index da1149a..b450b47 100644
> --- a/test/CodeGen/R600/load.vec.ll
> +++ b/test/CodeGen/R600/load.vec.ll
> @@ -23,3 +23,30 @@ define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i
>    store <4 x i32> %a, <4 x i32> addrspace(1)* %out
>    ret void
>  }
> +
> +; Load a v2i32 value from the constant address space.
> +; EG-CHECK: @load_const_addrspace_v2i32
> +; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4
> +; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0

Since these two VTX_READ instructions could appear in any order, you
should use the EG-CHECK-DAG directive.

-Tom

> +; SI-CHECK: @load_const_addrspace_v2i32
> +; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}}
> +
> +define void @load_const_addrspace_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(2)* %in) {
> +entry:
> +  %0 = load <2 x i32> addrspace(2)* %in
> +  store <2 x i32> %0, <2 x i32> addrspace(1)* %out
> +  ret void
> +}
> +
> +; Load a v4i32 value from the constant address space.
> +; EG-CHECK: @load_const_addrspace_v4i32
> +; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0
> +; SI-CHECK: @load_const_addrspace_v4i32
> +; SI-CHECK: BUFFER_LOAD_DWORDX4 VGPR{{[0-9]+}}
> +
> +define void @load_const_addrspace_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(2)* %in) {
> +entry:
> +  %0 = load <4 x i32> addrspace(2)* %in
> +  store <4 x i32> %0, <4 x i32> addrspace(1)* %out
> +  ret void
> +}
> -- 
> 1.8.1.2
>