[Mesa-dev] [PATCH] util: fix wrong shift val for a cpu feature detect

[Matt Turner]

On Wed, Mar 6, 2013 at 5:39 PM, Maxence Le Doré
<maxence.ledore at gmail.com> wrote:
> While I was trying to understand how cpu features detection works, I noticed
> that every was coherent except for the TSC ( Time Stamp Counter). I found
> many pages on the net that suggest that the right value for the
> corresponding shift would be 4 and not 8. Even the commented bitfields that
> represent the bit flag for each cpu feature seems to suggest that.
>
>
> From 17adc106ce2718343dd17750c928137441ef3086 Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?Maxence=20Le=20Dor=C3=A9?= <maxence.ledore at gmail.com>
> Date: Thu, 7 Mar 2013 02:30:03 +0100
> Subject: [PATCH] util: fix wrong shift val for a cpu feature detect
>
> ---
>  src/gallium/auxiliary/util/u_cpu_detect.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c
> b/src/gallium/auxiliary/util/u_cpu_detect.c
> index d7f0be4..0328051 100644
> --- a/src/gallium/auxiliary/util/u_cpu_detect.c
> +++ b/src/gallium/auxiliary/util/u_cpu_detect.c
> @@ -270,7 +270,7 @@ util_cpu_detect(void)
>               util_cpu_caps.x86_cpu_type = 8 + ((regs2[0] >> 20) & 255); /*
> use extended family (P4, IA64) */
>
>           /* general feature flags */
> -         util_cpu_caps.has_tsc    = (regs2[3] >>  8) & 1; /* 0x0000010 */
> +         util_cpu_caps.has_tsc    = (regs2[3] >>  4) & 1; /* 0x0000010 */
>           util_cpu_caps.has_mmx    = (regs2[3] >> 23) & 1; /* 0x0800000 */
>           util_cpu_caps.has_sse    = (regs2[3] >> 25) & 1; /* 0x2000000 */
>           util_cpu_caps.has_sse2   = (regs2[3] >> 26) & 1; /* 0x4000000 */
> --
> 1.7.9.5

Indeed, this matches Wikipedia [1] and even the comment on the same line. :)

Reviewed-by: Matt Turner <mattst88 at gmail.com>

[1] http://en.wikipedia.org/wiki/CPUID#EAX.3D1:_Processor_Info_and_Feature_Bits