[Mesa-dev] [PATCH 7/8] i965/vs: Use a send from a 2-register VGRF for shader time writes.

[Eric Anholt]

This will let us emit it later, after we're setting up MRFs for the
URB write.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp      |   24 ++++++++++++------------
 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |    3 +--
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index ac9b8c9..6891023 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -222,7 +222,7 @@ vec4_instruction::is_math()
 bool
 vec4_instruction::is_send_from_grf()
 {
-   return false;
+   return opcode == SHADER_OPCODE_SHADER_TIME_ADD;
 }
 
 bool
@@ -1246,20 +1246,20 @@ vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type,
    int shader_time_index = brw_get_shader_time_index(brw, prog, &vp->Base,
                                                      type);
 
-   int base_mrf = 6;
+   dst_reg dst =
+      dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 2));
 
-   dst_reg offset_mrf = dst_reg(MRF, base_mrf);
-   offset_mrf.type = BRW_REGISTER_TYPE_UD;
-   emit(MOV(offset_mrf, src_reg(shader_time_index * SHADER_TIME_STRIDE)));
+   dst_reg offset = dst;
+   dst_reg time = dst;
+   time.reg_offset++;
 
-   dst_reg time_mrf = dst_reg(MRF, base_mrf + 1);
-   time_mrf.type = BRW_REGISTER_TYPE_UD;
-   emit(MOV(time_mrf, src_reg(value)));
+   offset.type = BRW_REGISTER_TYPE_UD;
+   emit(MOV(offset, src_reg(shader_time_index * SHADER_TIME_STRIDE)));
 
-   vec4_instruction *inst;
-   inst = emit(SHADER_OPCODE_SHADER_TIME_ADD);
-   inst->base_mrf = base_mrf;
-   inst->mlen = 2;
+   time.type = BRW_REGISTER_TYPE_UD;
+   emit(MOV(time, src_reg(value)));
+
+   emit(SHADER_OPCODE_SHADER_TIME_ADD, dst_reg(), src_reg(dst));
 }
 
 bool
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 54f3efd..cb49a04 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -674,8 +674,7 @@ vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
       break;
 
    case SHADER_OPCODE_SHADER_TIME_ADD:
-      brw_shader_time_add(p, brw_message_reg(inst->base_mrf),
-                          SURF_INDEX_VS_SHADER_TIME);
+      brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
       break;
 
    default:
-- 
1.7.10.4