[Mesa-dev] [PATCH] R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics

[Christian König]

Am 21.03.2013 17:32, schrieb Michel Dänzer:
> From: Michel Dänzer <michel.daenzer at amd.com>
>
> Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g.
> manifested by failure of two piglit/glean tests and intermittent black
> patches in many apps.
>
> Tested on SI and RS880.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi]
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g]
>
> NOTE: This is a candidate for the Mesa stable branch.
>
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   lib/Target/R600/R600ISelLowering.cpp | 11 -----------
>   lib/Target/R600/R600ISelLowering.h   |  1 -
>   lib/Target/R600/R600Instructions.td  |  5 ++++-
>   lib/Target/R600/SIInstructions.td    |  3 +--
>   4 files changed, 5 insertions(+), 15 deletions(-)
>
> diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
> index a73691d..7bdba83 100644
> --- a/lib/Target/R600/R600ISelLowering.cpp
> +++ b/lib/Target/R600/R600ISelLowering.cpp
> @@ -58,7 +58,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
>     setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
>     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
>     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
> -  setOperationAction(ISD::FPOW, MVT::f32, Custom);
>   
>     setOperationAction(ISD::ROTL, MVT::i32, Custom);
>   
> @@ -316,7 +315,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
>     case ISD::SELECT: return LowerSELECT(Op, DAG);
>     case ISD::STORE: return LowerSTORE(Op, DAG);
>     case ISD::LOAD: return LowerLOAD(Op, DAG);
> -  case ISD::FPOW: return LowerFPOW(Op, DAG);
>     case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
>     case ISD::INTRINSIC_VOID: {
>       SDValue Chain = Op.getOperand(0);
> @@ -918,15 +916,6 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
>     return DAG.getMergeValues(Ops, 2, DL);
>   }
>   
> -SDValue R600TargetLowering::LowerFPOW(SDValue Op,
> -    SelectionDAG &DAG) const {
> -  DebugLoc DL = Op.getDebugLoc();
> -  EVT VT = Op.getValueType();
> -  SDValue LogBase = DAG.getNode(ISD::FLOG2, DL, VT, Op.getOperand(0));
> -  SDValue MulLogBase = DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), LogBase);
> -  return DAG.getNode(ISD::FEXP2, DL, VT, MulLogBase);
> -}
> -
>   /// XXX Only kernel functions are supported, so we can assume for now that
>   /// every function is a kernel function, but in the future we should use
>   /// separate calling conventions for kernel and non-kernel functions.
> diff --git a/lib/Target/R600/R600ISelLowering.h b/lib/Target/R600/R600ISelLowering.h
> index 5cb4b91..2c09acb 100644
> --- a/lib/Target/R600/R600ISelLowering.h
> +++ b/lib/Target/R600/R600ISelLowering.h
> @@ -59,7 +59,6 @@ private:
>     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
>     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
>     SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
> -  SDValue LowerFPOW(SDValue Op, SelectionDAG &DAG) const;
>     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
>     SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
>   
> diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
> index 8c50d54..a6daadf 100644
> --- a/lib/Target/R600/R600Instructions.td
> +++ b/lib/Target/R600/R600Instructions.td
> @@ -1141,6 +1141,7 @@ let Predicates = [isR600] in {
>     def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
>   
>     defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
> +  def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL, R600_Reg32>;
>     def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
>   
>     def : Pat<(fsqrt R600_Reg32:$src),
> @@ -1212,6 +1213,7 @@ def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
>   def SIN_eg : SIN_Common<0x8D>;
>   def COS_eg : COS_Common<0x8E>;
>   
> +def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL, R600_Reg32>;
>   def : SIN_PAT <SIN_eg>;
>   def : COS_PAT <COS_eg>;
>   def : Pat<(fsqrt R600_Reg32:$src),
> @@ -1540,13 +1542,14 @@ def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
>   def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
>   def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
>   def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
> -def LOG_IEEE_ : LOG_IEEE_Common<0x83>;
> +def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
>   def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
>   def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
>   def SIN_cm : SIN_Common<0x8D>;
>   def COS_cm : COS_Common<0x8E>;
>   } // End isVector = 1
>   
> +def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL, R600_Reg32>;
>   def : SIN_PAT <SIN_cm>;
>   def : COS_PAT <COS_cm>;
>   
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 05b04a9..dc75f01 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -1442,8 +1442,7 @@ def : Pat <
>   /********** ================== **********/
>   
>   /* llvm.AMDGPU.pow */
> -/* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
> -def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
> +def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32, VReg_32>;
>   
>   def : Pat <
>     (int_AMDGPU_div VSrc_32:$src0, VSrc_32:$src1),