[Mesa-dev] [PATCH] i965/gen7: Use WE_all mode when enabling channel masks for URB write.

[Kenneth Graunke]

On 03/23/2013 09:17 AM, Paul Berry wrote:
> Gen7 adds mask bits to the message header for a URB write which allow
> the write to apply only to certain channels.  We don't use this
> functionality, so to ensure that the entire write always occurs, we
> emit an OR instruction to set the mask bits.
>
> With the advent of geometry shaders, URB writes won't just happen at
> the end of a thread; they will happen in mid-thread too.  Thus, we can
> no longer rely on channel 0 being enabled, so we need to emit the OR
> instruction in WE_all mode to ensure that it is executed.
> ---
>   src/mesa/drivers/dri/i965/brw_eu_emit.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 992e784..2355626 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -2184,6 +2184,7 @@ void brw_urb_WRITE(struct brw_compile *p,
>         /* Enable Channel Masks in the URB_WRITE_HWORD message header */
>         brw_push_insn_state(p);
>         brw_set_access_mode(p, BRW_ALIGN_1);
> +      brw_set_mask_control(p, BRW_MASK_DISABLE);
>         brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5),
>   		       BRW_REGISTER_TYPE_UD),
>   	        retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),

Oh, yeah, that's a good idea.  Honestly, it should've been MASK_DISABLE 
to begin with, I just didn't know what I was doing when I wrote that 
code, and it happened to work out.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

I've always wondered what we -would- use that for.