[Mesa-dev] [PATCH 3/3] i965: Use Y-tiled blits to untile for cached mappings of miptrees.

[Eric Anholt]

Kenneth Graunke <kenneth at whitecape.org> writes:

> On 05/06/2013 04:41 PM, Eric Anholt wrote:
>> Fixes a regression in firefox's ReadScreenIntoImageSurface ->
>> glReadPixels() path with the introduction of Y tiling.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64213
>> ---
>>   src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
>> index 8970228..7f4cb4a 100644
>> --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
>> +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
>> @@ -1903,7 +1903,8 @@ intel_miptree_map_singlesample(struct intel_context *intel,
>>      else if (intel->has_llc &&
>>               !(mode & GL_MAP_WRITE_BIT) &&
>>               !mt->compressed &&
>> -            mt->region->tiling == I915_TILING_X &&
>> +            (mt->region->tiling == I915_TILING_X ||
>> +             (intel->gen >= 6 && mt->region->tiling == I915_TILING_Y)) &&
>>               mt->region->pitch < 32768) {
>>         intel_miptree_map_blit(intel, mt, map, level, slice);
>>      } else if (mt->region->tiling != I915_TILING_NONE &&
>
> This patch is fine, but the blitter can handle untiled buffers as well. 
> It might be even better (and simpler) as:
>
> (intel->gen >= 6 || mt->region->Tiling != I915_TILING_Y)
>
> That said, untiled buffers can also be mapped via the CPU rather than 
> the GTT with a fence, so maybe it's not as big of a deal.

The point of this path is to get an untiled buffer that can be mapped
via the CPU rather than the GTT with a fence.  If you don't take it,
you'll map with the CPU or the GTT based on tiling and LLC.

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