[Mesa-dev] [PATCH 3/5] intel: add layered parameter to update_renderbuffer_surface

[Jordan Justen]

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c  |    6 +++++-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |    3 +++
 src/mesa/drivers/dri/intel/intel_context.h        |    1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index bbe8579..efc15e9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1315,6 +1315,7 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 static void
 brw_update_renderbuffer_surface(struct brw_context *brw,
 				struct gl_renderbuffer *rb,
+				bool layered,
 				unsigned int unit)
 {
    struct intel_context *intel = &brw->intel;
@@ -1328,6 +1329,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    /* _NEW_BUFFERS */
    gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 
+   assert(!layered);
+
    if (rb->TexImage && !brw->has_surface_tile_offset) {
       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 
@@ -1424,7 +1427,8 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw)
    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 	 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
-	    intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
+	    intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
+	                                            ctx->DrawBuffer->Layered, i);
 	 } else {
 	    intel->vtbl.update_null_renderbuffer_surface(brw, i);
 	 }
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 435f9dc..6c01545 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -522,6 +522,7 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 static void
 gen7_update_renderbuffer_surface(struct brw_context *brw,
 				 struct gl_renderbuffer *rb,
+				 bool layered,
 				 unsigned int unit)
 {
    struct intel_context *intel = &brw->intel;
@@ -533,6 +534,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    /* _NEW_BUFFERS */
    gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 
+   assert(!layered);
+
    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
                                     8 * 4, 32, &brw->wm.surf_offset[unit]);
    memset(surf, 0, 8 * 4);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index c0f07ff..5420e76 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -196,6 +196,7 @@ struct intel_context
                                      unsigned surf_index);
       void (*update_renderbuffer_surface)(struct brw_context *brw,
 					  struct gl_renderbuffer *rb,
+					  bool layered,
 					  unsigned unit);
       void (*update_null_renderbuffer_surface)(struct brw_context *brw,
 					       unsigned unit);
-- 
1.7.10.4