[Mesa-dev] [PATCH 10/12] i965/gen7+: Resolve color buffers when necessary.
Paul Berry
stereotype441 at gmail.com
Tue May 21 16:52:14 PDT 2013
Resolve color buffers that have been fast-color cleared:
1. before texturing from the buffer
2. before using the buffer as the source in a blorp blit
3. before mapping the buffer's miptree
4. before accessing the buffer using the hardware blitter
Cases 1 and 2 happen in the functions brw_predraw_resolve_buffers()
and brw_blorp_blit_miptrees(), respectively. Cases 3 and 4 are
handled by the intel_miptree_get_region() function.
In order to make sure that intel_miptree_get_region() doesn't try to
resolve a buffer during emission of state commands, this patch also
adds a new boolean, brw->state_emission_in_progress, which is set to
true during brw_upload_state() and brw_blorp_exec().
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 7 +++++++
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 8 ++++++++
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_draw.c | 6 +++++-
src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ++++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 2 +-
7 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index c6019d1..984b2a1 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -172,6 +172,7 @@ void
brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
{
struct brw_context *brw = brw_context(&intel->ctx);
+ brw->state_emission_in_progress = true;
switch (intel->gen) {
case 6:
@@ -186,6 +187,8 @@ brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
break;
}
+ brw->state_emission_in_progress = false;
+
if (unlikely(intel->always_flush_batch))
intel_batchbuffer_flush(intel);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c3ef054..7a47632 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -132,6 +132,13 @@ brw_blorp_blit_miptrees(struct intel_context *intel,
int dst_x1, int dst_y1,
bool mirror_x, bool mirror_y)
{
+ /* Get ready to blit. This includes depth resolving the src and dst
+ * buffers if necessary. Note: it's not necessary to do a color resolve on
+ * the destination buffer because we use the standard render path to render
+ * to destination color buffers, and the standard render path is
+ * fast-color-aware.
+ */
+ intel_miptree_resolve_color(intel, src_mt);
intel_miptree_slice_resolve_depth(intel, src_mt, src_level, src_layer);
intel_miptree_slice_resolve_depth(intel, dst_mt, dst_level, dst_layer);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index a598dff..d397917 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -503,6 +503,14 @@ void
brw_blorp_resolve_color(struct intel_context *intel, struct intel_mipmap_tree *mt)
{
struct brw_context *brw = brw_context(&intel->ctx);
+
+ /* We can't safely resolve the render target while emitting 3D state. If
+ * the following assertion fails, that indicates that the render target
+ * resolve should have been performed earlier, e.g. by
+ * brw_predraw_resolve_buffers().
+ */
+ assert(!brw->state_emission_in_progress);
+
brw_blorp_rt_resolve_params params(brw, mt);
brw_blorp_exec(intel, ¶ms);
mt->mcs_state = INTEL_MCS_STATE_RESOLVED;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index ee7bf33..1961c01 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1131,6 +1131,8 @@ struct brw_context
int max_entries;
double report_time;
} shader_time;
+
+ bool state_emission_in_progress;
};
/*======================================================================
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 8c37e0b..d8c1ecf 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -41,6 +41,7 @@
#include "swrast_setup/swrast_setup.h"
#include "drivers/common/meta.h"
+#include "brw_blorp.h"
#include "brw_draw.h"
#include "brw_defines.h"
#include "brw_context.h"
@@ -310,7 +311,9 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
if (depth_irb)
intel_renderbuffer_resolve_hiz(intel, depth_irb);
- /* Resolve depth buffer of each enabled depth texture. */
+ /* Resolve depth buffer of each enabled depth texture, and color buffer of
+ * each fast-clear-enabled color texture.
+ */
for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) {
if (!ctx->Texture.Unit[i]._ReallyEnabled)
continue;
@@ -318,6 +321,7 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
if (!tex_obj || !tex_obj->mt)
continue;
intel_miptree_all_slices_resolve_depth(intel, tex_obj->mt);
+ intel_miptree_resolve_color(intel, tex_obj->mt);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 85c01e1..a91e837 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -472,6 +472,8 @@ void brw_upload_state(struct brw_context *brw)
intel_check_front_buffer_rendering(intel);
+ brw->state_emission_in_progress = true;
+
if (unlikely(INTEL_DEBUG)) {
/* Debug version which enforces various sanity checks on the
* state flags which are generated and checked to help ensure
@@ -510,6 +512,8 @@ void brw_upload_state(struct brw_context *brw)
}
}
+ brw->state_emission_in_progress = false;
+
if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
brw_update_dirty_count(mesa_bits, state->mesa);
brw_update_dirty_count(brw_bits, state->brw);
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index f4ef4e6..56e5c88 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -802,7 +802,7 @@ intel_miptree_get_region(struct intel_context *intel,
case INTEL_MIPTREE_ACCESS_BLIT:
case INTEL_MIPTREE_ACCESS_MAP:
case INTEL_MIPTREE_ACCESS_TEX:
- /* TODO: perform a render target resolve. */
+ intel_miptree_resolve_color(intel, mt);
break;
case INTEL_MIPTREE_ACCESS_SHARED:
/* TODO: resolve and then discard MCS buffer since fast color clears are
--
1.8.2.3
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