[Mesa-dev] [PATCH 1/2] softpipe: disambiguate TILE_SIZE / TEX_TILE_SIZE
sroland at vmware.com
sroland at vmware.com
Tue May 21 18:15:10 PDT 2013
From: Roland Scheidegger <sroland at vmware.com>
These can be different (just like NUM_TEX_TILE_ENTRIES / NUM_ENTRIES),
though currently they aren't.
---
src/gallium/drivers/softpipe/sp_tex_sample.c | 28 +++++++++++-----------
src/gallium/drivers/softpipe/sp_tex_tile_cache.c | 28 +++++++++++-----------
src/gallium/drivers/softpipe/sp_tex_tile_cache.h | 20 ++++++++--------
3 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c b/src/gallium/drivers/softpipe/sp_tex_sample.c
index 1550199..2c7f17f 100644
--- a/src/gallium/drivers/softpipe/sp_tex_sample.c
+++ b/src/gallium/drivers/softpipe/sp_tex_sample.c
@@ -580,10 +580,10 @@ get_texel_2d_no_border(const struct sp_sampler_view *sp_sview,
union tex_tile_address addr, int x, int y)
{
const struct softpipe_tex_cached_tile *tile;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
- y %= TILE_SIZE;
- x %= TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
+ y %= TEX_TILE_SIZE;
+ x %= TEX_TILE_SIZE;
tile = sp_get_cached_tile_tex(sp_sview->cache, addr);
@@ -722,10 +722,10 @@ get_texel_quad_2d_no_border_single_tile(const struct sp_sampler_view *sp_sview,
{
const struct softpipe_tex_cached_tile *tile;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
- y %= TILE_SIZE;
- x %= TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
+ y %= TEX_TILE_SIZE;
+ x %= TEX_TILE_SIZE;
tile = sp_get_cached_tile_tex(sp_sview->cache, addr);
@@ -777,11 +777,11 @@ get_texel_3d_no_border(const struct sp_sampler_view *sp_sview,
{
const struct softpipe_tex_cached_tile *tile;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
addr.bits.z = z;
- y %= TILE_SIZE;
- x %= TILE_SIZE;
+ y %= TEX_TILE_SIZE;
+ x %= TEX_TILE_SIZE;
tile = sp_get_cached_tile_tex(sp_sview->cache, addr);
@@ -917,8 +917,8 @@ img_filter_2d_linear_repeat_POT(struct sp_sampler_view *sp_sview,
{
unsigned xpot = pot_level_size(sp_sview->xpot, level);
unsigned ypot = pot_level_size(sp_sview->ypot, level);
- unsigned xmax = (xpot - 1) & (TILE_SIZE - 1); /* MIN2(TILE_SIZE, xpot) - 1; */
- unsigned ymax = (ypot - 1) & (TILE_SIZE - 1); /* MIN2(TILE_SIZE, ypot) - 1; */
+ unsigned xmax = (xpot - 1) & (TEX_TILE_SIZE - 1); /* MIN2(TEX_TILE_SIZE, xpot) - 1; */
+ unsigned ymax = (ypot - 1) & (TEX_TILE_SIZE - 1); /* MIN2(TEX_TILE_SIZE, ypot) - 1; */
union tex_tile_address addr;
int c;
diff --git a/src/gallium/drivers/softpipe/sp_tex_tile_cache.c b/src/gallium/drivers/softpipe/sp_tex_tile_cache.c
index af1024d..b0d8a18 100644
--- a/src/gallium/drivers/softpipe/sp_tex_tile_cache.c
+++ b/src/gallium/drivers/softpipe/sp_tex_tile_cache.c
@@ -50,7 +50,7 @@ sp_create_tex_tile_cache( struct pipe_context *pipe )
uint pos;
/* make sure max texture size works */
- assert((TILE_SIZE << TEX_ADDR_BITS) >= (1 << (SP_MAX_TEXTURE_2D_LEVELS-1)));
+ assert((TEX_TILE_SIZE << TEX_ADDR_BITS) >= (1 << (SP_MAX_TEXTURE_2D_LEVELS-1)));
tc = CALLOC_STRUCT( softpipe_tex_tile_cache );
if (tc) {
@@ -212,7 +212,7 @@ sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
if (addr.value != tile->addr.value) {
- /* cache miss. Most misses are because we've invaldiated the
+ /* cache miss. Most misses are because we've invalidated the
* texture cache previously -- most commonly on binding a new
* texture. Currently we effectively flush the cache on texture
* bind.
@@ -265,26 +265,26 @@ sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
*/
if (!zs && util_format_is_pure_uint(tc->format)) {
pipe_get_tile_ui_format(tc->tex_trans, tc->tex_trans_map,
- addr.bits.x * TILE_SIZE,
- addr.bits.y * TILE_SIZE,
- TILE_SIZE,
- TILE_SIZE,
+ addr.bits.x * TEX_TILE_SIZE,
+ addr.bits.y * TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
tc->format,
(unsigned *) tile->data.colorui);
} else if (!zs && util_format_is_pure_sint(tc->format)) {
pipe_get_tile_i_format(tc->tex_trans, tc->tex_trans_map,
- addr.bits.x * TILE_SIZE,
- addr.bits.y * TILE_SIZE,
- TILE_SIZE,
- TILE_SIZE,
+ addr.bits.x * TEX_TILE_SIZE,
+ addr.bits.y * TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
tc->format,
(int *) tile->data.colori);
} else {
pipe_get_tile_rgba_format(tc->tex_trans, tc->tex_trans_map,
- addr.bits.x * TILE_SIZE,
- addr.bits.y * TILE_SIZE,
- TILE_SIZE,
- TILE_SIZE,
+ addr.bits.x * TEX_TILE_SIZE,
+ addr.bits.y * TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
tc->format,
(float *) tile->data.color);
}
diff --git a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
index b55c493..0ea82b3 100644
--- a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
+++ b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
@@ -40,11 +40,11 @@ struct softpipe_tex_tile_cache;
/**
* Cache tile size (width and height). This needs to be a power of two.
*/
-#define TILE_SIZE_LOG2 6
-#define TILE_SIZE (1 << TILE_SIZE_LOG2)
+#define TEX_TILE_SIZE_LOG2 6
+#define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
-#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TILE_SIZE_LOG2)
+#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2)
#define TEX_Z_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1)
/**
@@ -67,9 +67,9 @@ struct softpipe_tex_cached_tile
{
union tex_tile_address addr;
union {
- float color[TILE_SIZE][TILE_SIZE][4];
- unsigned int colorui[TILE_SIZE][TILE_SIZE][4];
- int colori[TILE_SIZE][TILE_SIZE][4];
+ float color[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+ unsigned int colorui[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+ int colori[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
} data;
};
@@ -120,7 +120,7 @@ sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
extern const struct softpipe_tex_cached_tile *
sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
- union tex_tile_address addr );
+ union tex_tile_address addr );
static INLINE union tex_tile_address
tex_tile_address( unsigned x,
@@ -132,8 +132,8 @@ tex_tile_address( unsigned x,
union tex_tile_address addr;
addr.value = 0;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
addr.bits.z = z;
addr.bits.face = face;
addr.bits.level = level;
@@ -145,7 +145,7 @@ tex_tile_address( unsigned x,
*/
static INLINE const struct softpipe_tex_cached_tile *
sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
- union tex_tile_address addr )
+ union tex_tile_address addr )
{
if (tc->last_tile->addr.value == addr.value)
return tc->last_tile;
--
1.7.9.5
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