[Mesa-dev] [PATCH] i965: Fix 'SIMD16 only' dispatch of fragment shader in case of sample shading

[Anuj Phogat]

This patch make changes to correctly set up the Dispatch GRF Start
Register in case of 'SIMD16 only' FS dispatch.

This fixes an issue of incorrect rendering on dolphin emulator with
GL_SAMPLE_SHADING enabled.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
 src/mesa/drivers/dri/i965/gen6_wm_state.c | 19 +++++++++++++------
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 19 ++++++++++++-------
 2 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 42d8789..1604681 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -146,10 +146,6 @@ upload_wm_state(struct brw_context *brw)
    /* CACHE_NEW_SAMPLER */
    dw2 |= (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
            GEN6_WM_SAMPLER_COUNT_SHIFT;
-   dw4 |= (brw->wm.prog_data->first_curbe_grf <<
-	   GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
-   dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
-	   GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 
    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 
@@ -166,11 +162,22 @@ upload_wm_state(struct brw_context *brw)
 
    if (brw->wm.prog_data->prog_offset_16) {
       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
-      if (min_inv_per_frag == 1)
+
+      if (min_inv_per_frag == 1) {
          dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
+         dw4 |= (brw->wm.prog_data->first_curbe_grf <<
+                 GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
+         dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+                 GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
+      } else
+         dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+                GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
    }
-   else
+   else {
       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
+      dw4 |= (brw->wm.prog_data->first_curbe_grf <<
+              GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
+   }
 
    /* CACHE_NEW_WM_PROG | _NEW_COLOR */
    if (brw->wm.prog_data->dual_src_blend &&
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 58a6438..f35079f 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -230,16 +230,21 @@ upload_ps_state(struct brw_context *brw)
 
    if (brw->wm.prog_data->prog_offset_16) {
       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
-      if (min_inv_per_frag == 1)
+      if (min_inv_per_frag == 1) {
          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
+         dw5 |= (brw->wm.prog_data->first_curbe_grf <<
+                 GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+         dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+                 GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
+      } else
+         dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+                 GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
    }
-   else
+   else {
       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
-
-   dw5 |= (brw->wm.prog_data->first_curbe_grf <<
-	   GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
-   dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
-	   GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
+      dw5 |= (brw->wm.prog_data->first_curbe_grf <<
+              GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+   }
 
    BEGIN_BATCH(8);
    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
-- 
1.8.1.4