[Mesa-dev] [PATCH 08/18] i965: Wire up initial support for DRI_RENDERER_QUERY extension
Daniel Vetter
daniel at ffwll.ch
Fri Nov 8 00:21:55 PST 2013
On Thu, Nov 07, 2013 at 04:23:12PM -0800, Ian Romanick wrote:
> On 11/07/2013 01:33 PM, Daniel Vetter wrote:
> > On Sat, Oct 12, 2013 at 12:10 AM, Ian Romanick <idr at freedesktop.org> wrote:
> >> + /* Once a batch uses more than 75% of the maximum mappable size, we
> >> + * assume that there's some fragmentation, and we start doing extra
> >> + * flushing, etc. That's the big cliff apps will care about.
> >> + *
> >> + * Can only map 2G onto the GPU through the GTT.
> >> + */
> >> + const unsigned gpu_mappable_megabytes = 2 * 1024 * 3 / 4;
> >
> > We have an ioctl to tell you that, since it's not really 2G on really
> > old stuff. And will probably change on newer platforms. Also, using
> > that ioctl allows the kernel to limit your usage in case the available
> > ram is less than the virtual size of the gtt (atm we don't bother with
> > that much cleverness, but probably will in the future). See
> > DRM_IOCTL_I915_GEM_GET_APERTURE in libdrm (it's unfortunately not
> > exposed through any libdrm function afaics.
>
> This only does GEN4+. i915 and earlier chips are handled in the
> previous patch, which uses drmAgpSize. Should that be used here too?
Oops, didn't spot that. But still original gen4 has only 512M and if you
look sharply at the bdw code you'll see it currently claims 4G, with
promise for more (64b relocs and all). The ioctl also gives you the size
in u64, so it's future-proof.
Also wrt drmAgpSize for gen2/3 that's the wrong size - it uses the
horribly agp legacy crap we unfortunately still have hanging around due to
XvMC bogosity on gen3. But already on gen2 and some gen3 where we don't
care this won't work and 3.14 has a patch from Ville to disable it
everywhere. So that needs to change to the gem aperture ioctl, too.
That agp layer desperately needs to die, so please don't add new uses to
extend its lifetime for another 5 years ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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