[Mesa-dev] [PATCH 2/3] i965/fs: Emit compressed 3-source instructions on Haswell.
Matt Turner
mattst88 at gmail.com
Sat Nov 16 16:19:10 PST 2013
For commit 4df56177 Paul discovered that the hardware restriction that
Align16 instructions cannot be compressed was lifted on Haswell. This
has prevented us from emitting compressed three-source instructions.
For added confirmation, the bspec lists a work around called
WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable
since very early Haswell silicon.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index cc58ff2..a97a016 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1404,7 +1404,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_MAD:
assert(brw->gen >= 6);
brw_set_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16) {
+ if (dispatch_width == 16 && !brw->is_haswell) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_MAD(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1419,7 +1419,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_LRP:
assert(brw->gen >= 6);
brw_set_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16) {
+ if (dispatch_width == 16 && !brw->is_haswell) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_LRP(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1516,7 +1516,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_BFE:
assert(brw->gen >= 7);
brw_set_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16) {
+ if (dispatch_width == 16 && !brw->is_haswell) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_BFE(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
--
1.8.3.2
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