[Mesa-dev] [PATCH 0/2] i965/gen7: vertical alignment fixes.
eric at anholt.net
Sun Nov 17 12:29:46 PST 2013
Paul Berry <stereotype441 at gmail.com> writes:
> While working on patch b4c3b83 (i965: Fix vertical alignment for
> multisampled buffers) I noticed that we were failing to follow another
> alignment rule: on gen7, render targets using Y tiling must have a
> vertical alignment of 4. This patch series ensures that we follow
> that rule by preferring a vertical alignment of 4 the hardware allows
> it (patch 1), and disallowing Y tiling of renderable surfaces when the
> hardware doesn't allow an alignment of 4 (patch 2).
> I'm not aware of any hardware misbehaviour resulting from our previous
> failure to follow this alignment rule, so I'm going to recommend that
> these patches *not* be backported to stable branches.
Reviewed-by: Eric Anholt <eric at anholt.net>
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