[Mesa-dev] [PATCH 27/27] i965: Enable the AMD_performance_monitor extension on Gen5+.

Eric Anholt eric at anholt.net
Mon Nov 18 17:22:01 PST 2013

Kenneth Graunke <kenneth at whitecape.org> writes:

> On 11/18/2013 10:33 AM, Eric Anholt wrote:
>> Kenneth Graunke <kenneth at whitecape.org> writes:
>>> XXX: Gen6+ needs to be predicated on register writes.
>>> our register write checking function doesn't work on Gen6.
>> Even if you can just enable it on gen7, this series is:
>> Reviewed-by: Eric Anholt <eric at anholt.net>
> Now I'm confused.  I thought you and Carl found regressions in patch 3
> (the tri-state ring enum patch), and that you basically NAK'd patch 04
> because it adds code to BEGIN_BATCH.
> I had thought I needed to rewrite patch 4 before I could upstream this.
>  Please clarify.

We found some slight flushing behavior change in patch 3, which we
talked over and I thought you'd squashed in the fix for already (the
missed true/false -> *_RING).

As far as patch 4: I'd almost always rather avoid BEGIN_BATCH overhead
since we call it so much, but the last other solution we talked about
(explicit ring switching) seemed like a scary maintenance problem
because you wouldn't notice when you forgot to add a switch to render,
since the ring's almost always in render already anyway.
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