[Mesa-dev] [PATCH 1/2] i965/blorp: Update language for fast color clear non-msrt restriction

[Chad Versace]

In an older BSpec, the restriction was documented for HSW GT3. The
current BSpec lists the restriction in a table for IVB, HSW, and VLVT.
Only the gods know to which hardware the restriction really applies.

CC: Paul Berry <stereotype441 at gmail.com>
CC: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 02ec273..63d83d7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -267,11 +267,16 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
 
       if (brw->is_haswell && brw->gt == 3) {
          /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
-          * Backend > MCS Buffer for Render Target(s) [DevIVB+]:
-          * [DevHSW:GT3]: Clear rectangle must be aligned to two times the
-          * number of pixels in the table shown below...
-          * x_align, y_align values computed above are the relevant entries
-          * in the referred table.
+          * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
+          * Clear of Non-MultiSampled Render Target Restrictions":
+          *
+          *   [IVB, VLVT, HSW]: Clear rectangle must be aligned to two times
+          *   the number of pixels in the table shown below...  x_align,
+          *   y_align values computed above are the relevant entries in the
+          *   referred table.
+          *
+          * Note: An older BSpec documented the above restriction for only
+          * HSW GT3.
           */
          x0 = ROUND_DOWN_TO(x0, 2 * x_align);
          y0 = ROUND_DOWN_TO(y0, 2 * y_align);
-- 
1.8.4