[Mesa-dev] [PATCH 05/16] i965/gen7.5: Implement MI_RS_STORE_DATA_IMM workaround for 3DPRIMITIVE commands

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_draw.c     |   14 ++++++++++++++
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |   14 ++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 549f9d0a..9b3e07f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -207,6 +207,20 @@ static void brw_emit_prim(struct brw_context *brw,
    }
 
    if (brw->gen >= 7) {
+      /* If resource streamer is enabled, an MI_RS_STORE_DATA_IMM with Resource
+       * Streamer Flush set must be programmed prior to a 3DPRIMITIVE command.
+       */
+      if (brw->has_resource_streamer) {
+         BEGIN_BATCH(4);
+         OUT_BATCH(MI_RS_STORE_DATA_IMM |
+                   (1 << 21) |  /* rs flush */
+                   (4 - 2));
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+         ADVANCE_BATCH();
+      }
+      
       BEGIN_BATCH(7);
       OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
       OUT_BATCH(hw_prim | vertex_access_type);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 9df3d92..4d1a65e 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -803,6 +803,20 @@ static void
 gen7_blorp_emit_primitive(struct brw_context *brw,
                           const brw_blorp_params *params)
 {
+   /* If resource streamer is enabled, an MI_RS_STORE_DATA_IMM with Resource
+    * Streamer Flush set must be programmed prior to a 3DPRIMITIVE command.
+    */
+   if (brw->has_resource_streamer) {
+      BEGIN_BATCH(4);
+      OUT_BATCH(MI_RS_STORE_DATA_IMM |
+                (1 << 21) |  /* rs flush */
+                (4 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   }
+
    BEGIN_BATCH(7);
    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
-- 
1.7.9.5