[Mesa-dev] [PATCH 16/16] i965/gen7.5: Flush on-chip binding table to pool

[Abdiel Janulgue]

Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.

Note that the the binding table pointer offset is relative to the binding table
pool base address when resource streamer instead of the surface state base address.

In addition, 3DSTATE_BINDING_TABLE_POINTERS_* expects btp offsets of up to 64k when
resource streamer hardware binding tables are enabled. However the bt entry within
the command only allows until 32k. Therefore, ensure that offset fits within the
highest bit of the command.

v3: Update to include 3DSTATE_BINDING_TABLE_POINTERS_GS

Cc: Paul Berry <stereotype441 at gmail.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Chad Versace <chad.versace at linux.intel.com>
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |    4 +++-
 src/mesa/drivers/dri/i965/gen7_gs_state.c |    3 ++-
 src/mesa/drivers/dri/i965/gen7_vs_state.c |    3 ++-
 src/mesa/drivers/dri/i965/gen7_wm_state.c |    3 ++-
 4 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 031e21e..f2e58a0 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -602,7 +602,9 @@ gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 {
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
-   OUT_BATCH(wm_bind_bo_offset);
+   /* For RS: fit maximum 64k binding table offset within high bits */
+   OUT_BATCH(brw->hw_bt_pool ? wm_bind_bo_offset >> 1
+             : wm_bind_bo_offset);
    ADVANCE_BATCH();
 }
 
diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c
index 3dd5896..1086b41 100644
--- a/src/mesa/drivers/dri/i965/gen7_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c
@@ -69,7 +69,8 @@ upload_gs_state(struct brw_context *brw)
    /* BRW_NEW_GS_BINDING_TABLE */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2));
-   OUT_BATCH(stage_state->bind_bo_offset);
+   OUT_BATCH(brw->hw_bt_pool ? stage_state->bind_bo_offset >> 1
+             : stage_state->bind_bo_offset);
    ADVANCE_BATCH();
 
    /* CACHE_NEW_SAMPLER */
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 4fd1913..c811826 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -77,7 +77,8 @@ upload_vs_state(struct brw_context *brw)
    /* BRW_NEW_VS_BINDING_TABLE */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
-   OUT_BATCH(stage_state->bind_bo_offset);
+   OUT_BATCH(brw->hw_bt_pool ? stage_state->bind_bo_offset >> 1
+             : stage_state->bind_bo_offset);
    ADVANCE_BATCH();
 
    /* CACHE_NEW_SAMPLER */
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 7ddeb6e..8477259 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -131,7 +131,8 @@ upload_ps_state(struct brw_context *brw)
    /* BRW_NEW_PS_BINDING_TABLE */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
-   OUT_BATCH(brw->wm.base.bind_bo_offset);
+   OUT_BATCH(brw->hw_bt_pool ? brw->wm.base.bind_bo_offset >> 1
+             : brw->wm.base.bind_bo_offset);
    ADVANCE_BATCH();
 
    /* CACHE_NEW_SAMPLER */
-- 
1.7.9.5