[Mesa-dev] [PATCH] i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB.

[Matt Turner]

On Tue, Oct 22, 2013 at 6:37 AM, Paul Berry <stereotype441 at gmail.com> wrote:
> In commit 800610f (i965/fs: Improve accuracy of dFdy() to match
> dFdx()) I unrolled the high-accuracy dFdy() computation from a single
> SIMD16 instruction to two SIMD8 instructions because of text I found
> in the i965 (gen4) PRM saying that instruction compression could not
> be used in align16 mode.  I couldn't find similar text in later
> hardware docs, and I observed problems trying to use instruction
> compression on align16 mode on Ivy Bridge, so I assumed that the
> restriction still applied and the associated documentation had simply
> been lost.
>
> After consultation with the hardware engineers, it turns out this is
> not the case.  In point of fact, the restriction was dropped in gen5,
> re-introduced in Ivy Bridge, and dropped again in Haswell.  The reason
> I didn't notice this is that in the Ivy Bridge documentation, the
> restriction was in a different section, and described using different
> language.

That's crazy, especially with the relevant text being dispersed
throughout the rest of the bspec. Nice work tracking this down.

Reviewed-by: Matt Turner <mattst88 at gmail.com>