[Mesa-dev] [PATCH] i965/gs: Set force_writemask_all when setting up g0.

[Kenneth Graunke]

On 10/22/2013 07:32 PM, Paul Berry wrote:
> All geometry shaders begin this instruction:
> 
>     mov(1) g0.2<1>:ud 0x0:ud { align1 }
> 
> which sets up GRF0 properly for scratch reads and writes.  Since this
> instruction has a SIMD size of 1, it will only have an effect if the
> first channel is enabled.  In practice, the hardware seems to always
> dispatch geometry shaders with the first channel enabled, but I can't
> find anything in the docs to guarantee that.
> 
> So to be on the safe side, set force_writemask_all on the instruction,
> which guarantees that it will have the desired effect regardless of
> which channels are enabled.
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> index 96636e8..0893c95 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> @@ -129,14 +129,15 @@ vec4_gs_visitor::emit_prolog()
>      */
>     this->current_annotation = "clear r0.2";
>     dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
> -   emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
> +   vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
> +   inst->force_writemask_all = true;
>  
>     /* Create a virtual register to hold the vertex count */
>     this->vertex_count = src_reg(this, glsl_type::uint_type);
>  
>     /* Initialize the vertex_count register to 0 */
>     this->current_annotation = "initialize vertex_count";
> -   vec4_instruction *inst = emit(MOV(dst_reg(this->vertex_count), 0u));
> +   inst = emit(MOV(dst_reg(this->vertex_count), 0u));
>     inst->force_writemask_all = true;
>  
>     if (c->control_data_header_size_bits > 0) {
> 

A very good idea.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>