[Mesa-dev] [PATCH 7/8] i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE
Eric Anholt
eric at anholt.net
Tue Oct 29 21:28:12 CET 2013
I'm going to be introducing gen7 variants, and the previous naming was
going to get confusing.
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
---
src/mesa/drivers/dri/i965/brw_defines.h | 7 +++----
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs.h | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 12 ++++++------
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 12 +++++++-----
src/mesa/drivers/dri/i965/brw_shader.cpp | 14 +++++---------
src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 ++--
10 files changed, 33 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index fbc787a..2248693 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -778,14 +778,15 @@ enum opcode {
SHADER_OPCODE_UNTYPED_ATOMIC,
SHADER_OPCODE_UNTYPED_SURFACE_READ,
+ SHADER_OPCODE_GEN4_SCRATCH_READ,
+ SHADER_OPCODE_GEN4_SCRATCH_WRITE,
+
FS_OPCODE_DDX,
FS_OPCODE_DDY,
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
FS_OPCODE_CINTERP,
FS_OPCODE_LINTERP,
- FS_OPCODE_SPILL,
- FS_OPCODE_UNSPILL,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD,
@@ -799,8 +800,6 @@ enum opcode {
FS_OPCODE_PLACEHOLDER_HALT,
VS_OPCODE_URB_WRITE,
- VS_OPCODE_SCRATCH_READ,
- VS_OPCODE_SCRATCH_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index f32a0aa..0c62040 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -766,11 +766,11 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case FS_OPCODE_FB_WRITE:
return 2;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
- case FS_OPCODE_UNSPILL:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
return 1;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
return inst->mlen;
- case FS_OPCODE_SPILL:
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
return 2;
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index fb1da4c..0512ab4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -523,8 +523,8 @@ private:
void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
bool negate_value);
- void generate_spill(fs_inst *inst, struct brw_reg src);
- void generate_unspill(fs_inst *inst, struct brw_reg dst);
+ void generate_scratch_write(fs_inst *inst, struct brw_reg src);
+ void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index e16d874..2172949 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -749,7 +749,7 @@ fs_generator::generate_discard_jump(fs_inst *inst)
}
void
-fs_generator::generate_spill(fs_inst *inst, struct brw_reg src)
+fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
{
assert(inst->mlen != 0);
@@ -761,7 +761,7 @@ fs_generator::generate_spill(fs_inst *inst, struct brw_reg src)
}
void
-fs_generator::generate_unspill(fs_inst *inst, struct brw_reg dst)
+fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
{
assert(inst->mlen != 0);
@@ -1579,12 +1579,12 @@ fs_generator::generate_code(exec_list *instructions)
generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
break;
- case FS_OPCODE_SPILL:
- generate_spill(inst, src[0]);
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+ generate_scratch_write(inst, src[0]);
break;
- case FS_OPCODE_UNSPILL:
- generate_unspill(inst, dst);
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
+ generate_scratch_read(inst, dst);
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index d2b1d2d..9b28d53 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -542,7 +542,8 @@ fs_visitor::emit_unspill(fs_inst *inst, fs_reg dst, uint32_t spill_offset,
int count)
{
for (int i = 0; i < count; i++) {
- fs_inst *unspill_inst = new(mem_ctx) fs_inst(FS_OPCODE_UNSPILL, dst);
+ fs_inst *unspill_inst =
+ new(mem_ctx) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_READ, dst);
unspill_inst->offset = spill_offset;
unspill_inst->ir = inst->ir;
unspill_inst->annotation = inst->annotation;
@@ -610,12 +611,12 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
loop_scale /= 10;
break;
- case FS_OPCODE_SPILL:
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
if (inst->src[0].file == GRF)
no_spill[inst->src[0].reg] = true;
break;
- case FS_OPCODE_UNSPILL:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
if (inst->dst.file == GRF)
no_spill[inst->dst.reg] = true;
break;
@@ -711,8 +712,9 @@ fs_visitor::spill_reg(int spill_reg)
spill_src.smear = -1;
for (int chan = 0; chan < inst->regs_written; chan++) {
- fs_inst *spill_inst = new(mem_ctx) fs_inst(FS_OPCODE_SPILL,
- reg_null_f, spill_src);
+ fs_inst *spill_inst =
+ new(mem_ctx) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE,
+ reg_null_f, spill_src);
spill_src.reg_offset++;
spill_inst->offset = subset_spill_offset + chan * reg_size;
spill_inst->ir = inst->ir;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 2c0248a..a351183 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -454,6 +454,11 @@ brw_instruction_name(enum opcode op)
case SHADER_OPCODE_TG4_OFFSET:
return "tg4_offset";
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
+ return "gen4_scratch_read";
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+ return "gen4_scratch_write";
+
case FS_OPCODE_DDX:
return "ddx";
case FS_OPCODE_DDY:
@@ -469,11 +474,6 @@ brw_instruction_name(enum opcode op)
case FS_OPCODE_LINTERP:
return "linterp";
- case FS_OPCODE_SPILL:
- return "spill";
- case FS_OPCODE_UNSPILL:
- return "unspill";
-
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
@@ -503,10 +503,6 @@ brw_instruction_name(enum opcode op)
case VS_OPCODE_URB_WRITE:
return "vs_urb_write";
- case VS_OPCODE_SCRATCH_READ:
- return "scratch_read";
- case VS_OPCODE_SCRATCH_WRITE:
- return "scratch_write";
case VS_OPCODE_PULL_CONSTANT_LOAD:
return "pull_constant_load";
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c1cfefa..3225912 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -258,9 +258,9 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
return 1;
case VS_OPCODE_PULL_CONSTANT_LOAD:
return 2;
- case VS_OPCODE_SCRATCH_READ:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
return 2;
- case VS_OPCODE_SCRATCH_WRITE:
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
return 3;
case GS_OPCODE_URB_WRITE:
case GS_OPCODE_THREAD_END:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 426f78c..30c2ca2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1149,11 +1149,11 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
generate_vs_urb_write(inst);
break;
- case VS_OPCODE_SCRATCH_READ:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
generate_scratch_read(inst, dst, src[0]);
break;
- case VS_OPCODE_SCRATCH_WRITE:
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
generate_scratch_write(inst, dst, src[0], src[1]);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 807c2f3..387e3c4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -294,8 +294,8 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
loop_scale /= 10;
break;
- case VS_OPCODE_SCRATCH_READ:
- case VS_OPCODE_SCRATCH_WRITE:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
for (int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF)
no_spill[inst->src[i].reg] = true;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 7f2ca95..16a188f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -229,7 +229,7 @@ vec4_visitor::SCRATCH_READ(dst_reg dst, src_reg index)
{
vec4_instruction *inst;
- inst = new(mem_ctx) vec4_instruction(this, VS_OPCODE_SCRATCH_READ,
+ inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_READ,
dst, index);
inst->base_mrf = 14;
inst->mlen = 2;
@@ -242,7 +242,7 @@ vec4_visitor::SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index)
{
vec4_instruction *inst;
- inst = new(mem_ctx) vec4_instruction(this, VS_OPCODE_SCRATCH_WRITE,
+ inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_WRITE,
dst, src, index);
inst->base_mrf = 13;
inst->mlen = 3;
--
1.8.4.rc3
More information about the mesa-dev
mailing list