[Mesa-dev] [PATCH 1/2] R600/SI: Add isDS helper function to SIInstrInfo

[Tom Stellard]

From: Tom Stellard <thomas.stellard at amd.com>

---
 lib/Target/R600/SIDefines.h            |  3 ++-
 lib/Target/R600/SIInstrFormats.td      |  3 +++
 lib/Target/R600/SIInstrInfo.cpp        |  4 ++++
 lib/Target/R600/SIInstrInfo.h          |  1 +
 lib/Target/R600/SILowerControlFlow.cpp | 12 +++++++-----
 5 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/lib/Target/R600/SIDefines.h b/lib/Target/R600/SIDefines.h
index f5445ad..259145d 100644
--- a/lib/Target/R600/SIDefines.h
+++ b/lib/Target/R600/SIDefines.h
@@ -14,7 +14,8 @@
 namespace SIInstrFlags {
 enum {
   MIMG = 1 << 3,
-  SMRD = 1 << 4
+  SMRD = 1 << 4,
+  DS   = 1 << 5
 };
 }
 
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
index 9576c05..59cc16b 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -19,12 +19,14 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
   field bits<1> LGKM_CNT = 0;
   field bits<1> MIMG = 0;
   field bits<1> SMRD = 0;
+  field bits<1> DS = 0;
 
   let TSFlags{0} = VM_CNT;
   let TSFlags{1} = EXP_CNT;
   let TSFlags{2} = LGKM_CNT;
   let TSFlags{3} = MIMG;
   let TSFlags{4} = SMRD;
+  let TSFlags{5} = DS;
 }
 
 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
@@ -308,6 +310,7 @@ class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let Inst{63-56} = vdst;
 
   let LGKM_CNT = 1;
+  let DS = 1;
 }
 
 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index e23eef3..356cf24 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -232,6 +232,10 @@ int SIInstrInfo::isSMRD(uint16_t Opcode) const {
   return get(Opcode).TSFlags & SIInstrFlags::SMRD;
 }
 
+bool SIInstrInfo::isDS(uint16_t Opcode) const {
+  return get(Opcode).TSFlags & SIInstrFlags::DS;
+}
+
 //===----------------------------------------------------------------------===//
 // Indirect addressing callbacks
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h
index 87b8063..4ccd4ce 100644
--- a/lib/Target/R600/SIInstrInfo.h
+++ b/lib/Target/R600/SIInstrInfo.h
@@ -49,6 +49,7 @@ public:
   virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
   int isMIMG(uint16_t Opcode) const;
   int isSMRD(uint16_t Opcode) const;
+  bool isDS(uint16_t Opcode) const;
 
   virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
 
diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
index a6c43bb..5a8836c 100644
--- a/lib/Target/R600/SILowerControlFlow.cpp
+++ b/lib/Target/R600/SILowerControlFlow.cpp
@@ -67,7 +67,7 @@ private:
 
   static char ID;
   const TargetRegisterInfo *TRI;
-  const TargetInstrInfo *TII;
+  const SIInstrInfo *TII;
 
   bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
 
@@ -407,7 +407,7 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
 }
 
 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
-  TII = MF.getTarget().getInstrInfo();
+  TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
   TRI = MF.getTarget().getRegisterInfo();
   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
@@ -425,6 +425,11 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
 
       Next = llvm::next(I);
       MachineInstr &MI = *I;
+
+      if (TII->isDS(MI.getOpcode())) {
+        NeedM0 = true;
+      }
+
       switch (MI.getOpcode()) {
         default: break;
         case AMDGPU::SI_IF:
@@ -487,9 +492,6 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
         case AMDGPU::DS_READ_B32:
           NeedWQM = true;
           // Fall through
-        case AMDGPU::DS_WRITE_B32:
-        case AMDGPU::DS_ADD_U32_RTN:
-          NeedM0 = true;
           break;
 
         case AMDGPU::V_INTERP_P1_F32:
-- 
1.8.1.5