[Mesa-dev] [PATCH 17/24] i965/gen7: Implement code generation for untyped surface read instructions.
Francisco Jerez
currojerez at riseup.net
Sun Sep 15 00:10:43 PDT 2013
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_eu.h | 8 +++++
src/mesa/drivers/dri/i965/brw_eu_emit.c | 56 +++++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs.h | 4 +++
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 18 ++++++++++
src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4.h | 4 +++
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 19 ++++++++++
9 files changed, 112 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index ccb4ce4..a04d82c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -771,6 +771,7 @@ enum opcode {
SHADER_OPCODE_SHADER_TIME_ADD,
SHADER_OPCODE_UNTYPED_ATOMIC,
+ SHADER_OPCODE_UNTYPED_SURFACE_READ,
FS_OPCODE_DDX,
FS_OPCODE_DDY,
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 212d916..83d830d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -431,6 +431,14 @@ brw_untyped_atomic(struct brw_compile *p,
GLuint msg_length,
GLuint response_length);
+void
+brw_untyped_surface_read(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg mrf,
+ GLuint bind_table_index,
+ GLuint msg_length,
+ GLuint response_length);
+
/***********************************************************************
* brw_eu_util.c:
*/
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f39bf99..7484649 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2527,6 +2527,62 @@ brw_untyped_atomic(struct brw_compile *p,
insn->header.access_mode == BRW_ALIGN_1);
}
+static void
+brw_set_dp_untyped_surface_read_message(struct brw_compile *p,
+ struct brw_instruction *insn,
+ GLuint bind_table_index,
+ GLuint msg_length,
+ GLuint response_length,
+ bool header_present)
+{
+ const unsigned dispatch_width =
+ (insn->header.execution_size == BRW_EXECUTE_16 ? 16 : 8);
+ const unsigned num_channels = response_length / (dispatch_width / 8);
+
+ if (p->brw->is_haswell) {
+ brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
+ msg_length, response_length,
+ header_present, false);
+
+ insn->bits3.gen7_dp.msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
+ } else {
+ brw_set_message_descriptor(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
+ msg_length, response_length,
+ header_present, false);
+
+ insn->bits3.gen7_dp.msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
+ }
+
+ if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (dispatch_width == 16)
+ insn->bits3.ud |= 1 << 12; /* SIMD16 mode */
+ else
+ insn->bits3.ud |= 2 << 12; /* SIMD8 mode */
+ }
+
+ insn->bits3.gen7_dp.binding_table_index = bind_table_index;
+
+ /* Set mask of 32-bit channels to drop. */
+ insn->bits3.ud |= (0xf & (0xf << num_channels)) << 8;
+}
+
+void
+brw_untyped_surface_read(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg mrf,
+ GLuint bind_table_index,
+ GLuint msg_length,
+ GLuint response_length)
+{
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+
+ brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
+ brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD));
+ brw_set_dp_untyped_surface_read_message(
+ p, insn, bind_table_index, msg_length, response_length,
+ insn->header.access_mode == BRW_ALIGN_1);
+}
+
/**
* This instruction is generated as a single-channel align1 instruction by
* both the VS and FS stages when using INTEL_DEBUG=shader_time.
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4f1a665..4afe37b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -739,6 +739,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case FS_OPCODE_SPILL:
return 2;
case SHADER_OPCODE_UNTYPED_ATOMIC:
+ case SHADER_OPCODE_UNTYPED_SURFACE_READ:
return 0;
default:
assert(!"not reached");
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 27a47fa..dcd489c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -561,6 +561,10 @@ private:
struct brw_reg atomic_op,
struct brw_reg surf_index);
+ void generate_untyped_surface_read(fs_inst *inst,
+ struct brw_reg dst,
+ struct brw_reg surf_index);
+
void mark_surface_used(unsigned surf_index);
void patch_discard_jumps_to_fb_writes();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index cf30fcb..c623bfe 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -1083,6 +1083,20 @@ fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
}
void
+fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
+ struct brw_reg surf_index)
+{
+ assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
+ surf_index.type == BRW_REGISTER_TYPE_UD);
+
+ brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
+ surf_index.dw1.ud,
+ inst->mlen, dispatch_width / 8);
+
+ mark_surface_used(surf_index.dw1.ud);
+}
+
+void
fs_generator::generate_code(exec_list *instructions)
{
int last_native_insn_offset = p->next_insn_offset;
@@ -1460,6 +1474,10 @@ fs_generator::generate_code(exec_list *instructions)
generate_untyped_atomic(inst, dst, src[0], src[1]);
break;
+ case SHADER_OPCODE_UNTYPED_SURFACE_READ:
+ generate_untyped_surface_read(inst, dst, src[0]);
+ break;
+
case FS_OPCODE_SET_SIMD4X2_OFFSET:
generate_set_simd4x2_offset(inst, dst, src[0]);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 590c0a5..6549d4e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -272,6 +272,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TXS:
return inst->header_present ? 1 : 0;
case SHADER_OPCODE_UNTYPED_ATOMIC:
+ case SHADER_OPCODE_UNTYPED_SURFACE_READ:
return 0;
default:
assert(!"not reached");
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 233f233..37e1da0 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -625,6 +625,10 @@ private:
struct brw_reg atomic_op,
struct brw_reg surf_index);
+ void generate_untyped_surface_read(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg surf_index);
+
void mark_surface_used(unsigned surf_index);
struct brw_context *brw;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 05c5806..003e503 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -853,6 +853,21 @@ vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
mark_surface_used(surf_index.dw1.ud);
}
+void
+vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg surf_index)
+{
+ assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
+ surf_index.type == BRW_REGISTER_TYPE_UD);
+
+ brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
+ surf_index.dw1.ud,
+ inst->mlen, 1);
+
+ mark_surface_used(surf_index.dw1.ud);
+}
+
/**
* Generate assembly for a Vec4 IR instruction.
*
@@ -1118,6 +1133,10 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
generate_untyped_atomic(inst, dst, src[0], src[1]);
break;
+ case SHADER_OPCODE_UNTYPED_SURFACE_READ:
+ generate_untyped_surface_read(inst, dst, src[0]);
+ break;
+
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
generate_unpack_flags(inst, dst);
break;
--
1.8.3.4
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